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參數(shù)資料
| 型號： | AKD4551.(AKD4551) |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Evaluation board Rev.C for AKD4551 |
| 中文描述： | 評價(jià)AKD4551板Rev.C |
| 文件頁數(shù)： | 5/17頁 |
| 文件大小： | 110K |
| 代理商： | AKD4551.(AKD4551) |
ASAHI KASEI
[AKD4551]
<KM062000>
’00/3
- 5 -
6) Evaluation of A/D using DIT. (Optical link)
PORT2 (TOTX176) is used. DIT generates audio bi-phase signal from received data and which is output
through optical connector (TOTX176). It is possible to connect AKM’s D/A converter evaluation boards on
the digital-amplifier which equips DIR input. In case of using external clock through a BNC connector (J5),
select EXT on JP12 (XTI) and short JP10 (XTE).
JP12
XTI
JP14
DIR
JP6
SCLK
DIR
ADC
JP8
LRCK
JP10
XTE
JP13
X_SCLK
DIR
ADC
D
X
E
OFF
ON
JP9
SDTI
DIR
ADC
64fs
32fs
7) All interfacing signals (MCLK, SCLK, LRCK) are fed from the external circuit through PORT1.
Under the following set-up, all external signals needed for the AK4551 to operate could be fed through
PORT1. In case of interfacing external sources to D/A converter, JP9 (SDTI) should be open. And in case of
using A/D data to externally, JP9 (SDTI) is set ADC side. When JP9 (SDTI) is open, the A/D data can be
output from the SDTO pin of PORT1 at the same time if JP7 (SDTO) is short.
JP12
XTI
JP14
DIR
JP6
SCLK
DIR
ADC
JP8
LRCK
JP10
XTE
JP13
X_SCLK
DIR
ADC
D
X
E
OFF
ON
JP9
SDTI
DIR
ADC
64fs
32fs
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