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參數(shù)資料
| 型號(hào)： | AKD4525 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 20BIT STEREO ADC & DAC WITH X TAL OSC |
| 中文描述： | 20位立體聲ADC |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 152K |
| 代理商： | AKD4525 |
ASAHI KASEI
[AK4525]
MS0053-E-00
2000/9
- 9 -
OPERATION OVERVIEW
n
System Clock
The master clock (MCLK) can be a crystal resonator placed across the XTI and XTO pin. The relationship between the
MCLK and the desired sample rate is defined in Table 1. The MCLK frequency is set by CMODE pin and the sampling
rate corresponds to 32kHz
～
48kHz.
In slave mode, the LRCK clock input must be synchronized with MCLK, however the phase is not critical. Internal
timing is synchronized to LRCK upon power-up. All external clocks must be present unless PDN= “L”, otherwise
excessive current may result from abnormal operation of internal dynamic logic.
MCLK
SCLK
fs
256fs
CMODE= “L”
8.1920MHz
11.2896MHz
12.2880MHz
384fs
CMODE= “H”
12.2880MHz
16.9344MHz
18.4320MHz
512fs
CMODE= “NC”
16.3840MHz
22.5792MHz
24.5760MHz
64fs
32.0kHz
44.1kHz
48.0kHz
2.0480MHz
2.8224MHz
3.0720MHz
Table 1. System Clock Example at normal speed
When the state of CMODE changes under operation, the AK4525 should be reset by PDN. At that case, the analog
outputs should be muted externally because some click noise may occur.
XTI
XTO
AK4525
Figure 1. X’tal resonator connection
External loading capacitor (
～
22pF to AGND for XTI/XTO) are required for a crystal oscillator. PDN should be held “L”
for 5ms to allow the X’tal oscillation to begin at power-up.
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