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參數(shù)資料
| 型號： | AKD4520 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 100dB 20Bit Stereo ADC & DAC |
| 中文描述： | 100dB的20位立體聲ADC |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 198K |
| 代理商： | AKD4520 |
ASAHI KASEI
[AK4520A]
0163-E-00
1997/3
- 9 -
OPERATION OVERVIEW
System Clock Input
The AK4520A with CMODE is used to select either MCLK=256fs or 384fs. The relationship between the
external clock applied to the MCLK input and the desired sample rate is defined in Table 1 . The LRCK clock
input must be synchronized with MCLK, however the phase is not critical. Internal timing is synchronized to
LRCK upon power-up or when the internal timing becomes out of phase. All external clocks must be present
unless both PWDA and PWAD ="L", otherwise excessive current may result from abnormal operation of
internal dynamic logic.
MCLK
256fs
CMODE="L"
8.1920MHz
11.2896MHz
12.2880MHz
SCLK
64fs
fs
384fs
CMODE="H"
12.2880MHz
16.9344MHz
18.4320MHz
Table 1 . System Clock Example
32fs
32.0kHz
44.1kHz
48.0kHz
2.048MHz
2.822MHz
3.072MHz
1.0240MHz
1.4112MHz
1.5360MHz
Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. Four serial data modes are
supported selected by the DIF0 and DIF1 pins as shown in Table 2 . In all modes the serial data is MSB-first,
2's compliment format is clocked on the falling edge of SCLK. For mode 3, if SCLK is 32fs, then the least
significant bits will be truncated.
Mode
DIF1
DIF0
SDTO(ADC)
SDTI(DAC)
L/R
SCLK
0
0
0
20bit, MSB justified
16bit, LSB justified
H/L
≥
32fs
1
0
1
20bit, MSB justified
20bit, LSB justified
H/L
≥
40fs
2
1
0
20bit, MSB justified
20bit, MSB justifie
H/L
≥
40fs
3
1
1
IIS(I2S)
IIS(I2S)
L/H
32fs or
≥
40fs
Table 2 . Serial Data Modes
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