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參數(shù)資料
| 型號(hào)： | AKD4520 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 100dB 20Bit Stereo ADC & DAC |
| 中文描述： | 100dB的20位立體聲ADC |
| 文件頁(yè)數(shù)： | 15/19頁(yè) |
| 文件大小： | 198K |
| 代理商： | AKD4520 |
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ASAHI KASEI
[AK4520A]
0163-E-00
1997/3
- 15 -
2. On-chip voltage reference
The differential Voltage between VREFH and VREFL sets the analog input/output range. VREFH pin is
normally connected to VA with a 0.1uF ceramic capacitor and VREFL pin is connected to AGND. VCOM is a
signal ground of this chip. An electrolytic capacitor 10uF parallel with a 0.1uF ceramic capacitor attached to
VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All
signals, especially clocks, should be kept away from the VREFH,VREFL and VCOM pins in order to avoid
unwanted coupling into the AK4520A.
3. Analog Inputs
The ADC inputs are differential and internally biased to the common voltage(VA/2) with 30k
(typ) resistance.
Figure 6 is a circuit example which analog signal is input by single end. the signal can be input from either
positive or negative input and the input signal range scales with the supply voltage and nominally 0.6 x
(VREFH-VREFL) Vpp. In case of single ended input, the distortion around full scale degrades compared with
differential input. Figure 9 is a circuit example which analog signal is input to both positive and negative input
and the input signal range scales with the supply voltage and nominally 0.3 x (VREFH-VREFL) Vpp. The
AK4520A can accept input voltages from AGND to VA. The ADC output data format is 2's complement The
output code is 7FFFFH(@20bit) for input above a positive full scale and 80000H(@20bit) for input below a
negative full scale. The ideal code is 00000H(@20bit) with no input signal. The DC offset is removed by the
internal HPF.
The AK4520A samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for
multiples of 64fs. A simple RC filter(fc=150kHz) may be used to attenuate any noise around 64fs and most
audio signals do not have significant energy at 64fs.
The AK4520A has tone noise with around -110dB on the ADC output. There are two methods of dropping VD
to 3V or adding a small DC offset at the ADC input to reduce the noise level. The evaluation board(AKD4520)
manual should be referred about the detail.
Figure 9 . Differential Input Buffer Example
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4520A-VF | 100dB 20Bit Stereo ADC & DAC |
| AK4520 | 100dB 20Bit Stereo ADC & DAC |
| AK4520A | 100dB 20Bit Stereo ADC & DAC |
| AKD4522 | EVALUATION BOARD REV.A FOR AK4522 |
| AKD4523 | EVALUATION BOARD REV.A FOR AK4523 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AKD4520A | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.B FOR AK4520A |
| AKD4522 | 制造商:AKM 制造商全稱:AKM 功能描述:20BIT STEREO ADC & DAC |
| AKD4523 | 制造商:AKM 制造商全稱:AKM 功能描述:20BIT STEREO ADC & DAC |
| AKD4524 | 制造商:AKM 制造商全稱:AKM 功能描述:24BIT 96KHZ AUDIO CODEC |
| AKD4525 | 制造商:AKM 制造商全稱:AKM 功能描述:20BIT STEREO ADC & DAC WITH X TAL OSC |
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