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參數(shù)資料
| 型號： | AKD4394.(AKD4394) |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Evaluation board Rev.C for AK4394 |
| 中文描述： | 評價AK4394板Rev.C |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 398K |
| 代理商： | AKD4394.(AKD4394) |
ASAHI KASEI
[AKD4394]
<KM063001>
4
’00/05
(3) Using AD converted data
AD converted data from AKM’s AD evaluation boards(AKD539X, AKD535X) is used through PORT1.
* In case of using external clock through a BNC connector, select EXT of JP9 and short JP1.
* In case of using the double speed sampling mode, select 1/2X of JP8 and set S2-2(DFS) on.
JP7
SD
JP6
LR
XTL/EXT
DIR
JP5
BI
XTL/EXT
DIR
CLK
JP9
DIR
EXT
XTL
JP8
CKDIV 1
2X
1X
JP4
BCP
INV
THR
JP2
CS8414
VDD
GND
JP1
JP14
CKDIV 2
1/2X
1X
XTL
Fig.5 Jumper set-up (A/D)
(4) All interface signals including master clock are fed externally.
Under the following set-up, MCLK, LRCK and SCLK signals needed for the D/A to operate could be fed through PORT1.
JP7
SD
JP6
LR
XTL/EXT
DIR
JP5
BI
XTL/EXT
DIR
CLK
JP9
DIR
EXT
XTL
JP8
CKDIV 1
2X
1X
JP4
BCP
INV
THR
JP2
CS8414
VDD
GND
JP1
JP14
CKDIV 2
1/2X
1X
XTL
Fig.6 Jumper set-up (ext.)
2. MCLK set-up
When the LRCK is fed from the 74HC4040 on the board, The ratio of MCLK to LRCK can be selected by JP8 and JP14.
JP14
1X
1X
1/2X
1/2X
JP8
1X
2X
1X
2X
X'tal
MCLK
12.288MHz
24.576MHz
12.288MHz
12.288MHz
fs
MCLK/LRCK
256
512
128
128
12.288MHz
24.576MHz
24.576MHz
49.152MHz
48kHz
48kHz
96kHz
96kHz
Table.1 set-up example
3. BICK set-up
When BICK is supplied from U1(74HC4040), either 32fs or 64fs could be
selected. Fig.8 shows 64fs mode. 64fs mode is recommended.
*Only mode 0(LSB justified 16bit mode) can correspond to 32fs.
Fig.7 Jumper Set-up (BCS)
JP3
BCS
64
32
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