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參數(shù)資料
| 型號： | AKD4394.(AKD4394) |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Evaluation board Rev.C for AK4394 |
| 中文描述： | 評價(jià)AK4394板Rev.C |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 398K |
| 代理商： | AKD4394.(AKD4394) |
ASAHI KASEI
[AKD4394]
<KM063001>
2
’00/05
<
External Analog Circuit (Rev.C)
The differential output circuit and LPF is implemented on board. The differential outputs of AK4394 is buffered by non-inverted
circuit and output via Cannon connector(differential output). LPF adds differential outputs. NJM5534D is used for op-amp on this
board that has low noise and high voltage torelance characteristics. Analog signal is output via Cannon and BNC connectors on the
board. The output level is about 2.94Vrms(typ@VREF=5.0V) by Cannon and 2Vrms(typ@VREF=5.0V) by BNC.
Fig.2 External Analog Filter
<
Operation sequence
1. Set up the jumpers for power supply.
[JP15(REG)] selects power supply for AVDD pin of AK4394.
short:
5V is supplied from regulator. (default)
Nothing should be connected to A5V jack.
open:
5V is supplied from A5V.
2. Set up the power supply lines.
+15V=15V, -15V=-15V:
Power supply for op-amp. AVDD of AK4394 is supplied from “+15V” through
regulator (JP15: short).
This jack is used when AVDD of AK4394 is supplied from this. In this case, JP15
should be open.
Power supply for logic circuit on this board.
Digital (set JP10 to VP),
A5V=5V:
DVDD=5V:
VP=3V
～
5.25V:
AGND=DGND=0V .
Each supply line should be distributed from the power unit.
3. Set up the evaluation modes by jumper pins and DIP switches.(See next item.)
4. Power on.(The AK4394 should be reset once by bringing PD "L" upon power-up.)
*SW1 resets the AK4394 during operation.
The AK4394 is reset at SW1="L" and exits resetting at SW1="H".
300
47u
300
AOUTL-
5
10n
3
220
10n
6
3
2
7
10u
0.1u
0.1u
10u
10u
NJM5534D
300
47u
300
10n
AOUTL+
5
3
220
10n
6
4
3
2
7
10u
0.1u
0.1u
10u
NJM5534D
3
2
1
1
1
0.1u
+
NJM5534D
0.1u
10u
+
100
4
3
4.7n
2
4.7n
620
620
430
7
+
+
+
+
-
+
-
+
+
+
-
+
Lch
-15
+15
6
4
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