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參數(shù)資料
| 型號(hào)： | AKD4380 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | EVALUATION BOARD REV.A FOR AK4380 |
| 中文描述： | 評(píng)價(jià)委員會(huì)版本A的AK4380 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大小： | 220K |
| 代理商： | AKD4380 |
ASAHI KASEI
[AKD4380]
<KM061500>
’00/04
- 2 -
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Analog output
Analog signal is output through BNC connectors on the board. And the output level of AK4380 is 3.45Vpp.
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Operation sequence
1) Set up the power supply lines.
[VA] (red)
[VD](red)
[AGND] (black)
[DGND] (black)
= 4.5
～
5.5V
= 4.5
～
5.5V
= 0V
= 0V
Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins and DIP switches.
(See the followings.)
3) Power on.
The AK4380 should be reset once bringing upon power-up
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Evaluation mode
Applicable evaluation modes
1) DIR (Optical Link and RCA) (default)
2) Using ROM data (AK43XX)
3) Using AKM’s evaluation board for ADC
4) Feeding all signals from external
1) DIR(Optical Link)
PORT3(TORX176) or J3(RCA) is used. All clock are supplied from CS8414(DIR). DIR generates MCLK,
BICK, LRCK and SDATA from the received data through optical connector (TORX176) or RCA connector.
Used for the evaluation using CD test disk. Nothing should be connected to PORT2. In case of using optical
connector (TORX176), select “OPT” on JP14(DIR/RX). In case of using RCA connector, select “RX”.
JP12
MCLK
JP11
DIR
JP3
BICK
DIR
ADC
JP4
LRCK
JP10
DIR_DATA
JP9
SDTI
DIR
ADC
D
X
E
GND
VD
DATA
GND
JP13
XTE
2) Ideal sine wave generated by ROM data
Connect the AKD43XX with PORT2(ADC/ROM). AKD4380 sends MCLK to AKD43XX, and receives LRCK,
BICK and SDATA. In case of using external master clock through a BNC connector, select “BNC” on
JP12(MCLK) and short JP13(XTE).
JP12
MCLK
JP11
DIR
JP3
BICK
DIR
ADC
JP4
LRCK
JP10
DIR_DATA
JP9
SDTI
DIR
ADC
D
X
E
GND
VD
DATA
GND
JP13
XTE
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| AKD4380/EVAL-BOARD | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
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