參數(shù)資料
型號(hào): AK7712A-VT
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:8; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-8 RoHS Compliant: No
中文描述: 內(nèi)置20位ADC / DAC的尖端音頻DSP
文件頁(yè)數(shù): 17/87頁(yè)
文件大小: 968K
代理商: AK7712A-VT
ASAHI KASEI
[AK7712A-VT]
0180-E-02
1997/12
- 17 -
1) Audio Interface Timing
(AVDD=DVDD,AVB,DVB=5.0V
±
5%,Ta=25
°
C;
Master clock 16.9344MHz,XTI=384fs[fs=44.1kHz]; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Slave mode
BCLK cycle
BCLK pulse width Low
pulse width High
Time from BCLK"
" to LRCK (note 1)
Delay time from LRCK to DOUT(MSB)
Delay time from BCLK"
" to DOUT
Latch hold time of SDIN
Latch setup time of SDIN
Master mode
BCLK cycle
Duty cycle
BCLK pulse width Low
pulse width High
Time from BCLK"
" to LRCK
Delay time from LRCK to DOUT(MSB)
Delay time from BCLK"
" to DOUT
Latch hold time of SDIN
Latch set Up time of SDIN
note 1 : This standard value is provided for not to be overlapped the edge of LRCK and BCLK"
" each other.
t
BLK
t
BLKL
t
BLKH
t
BLR
t
LRD
t
BLKD
t
DINH
t
DINS
t
BLK
t
BLKL
t
BLKH
t
BLR
t
LRD
t
BLKD
t
DINH
t
DINS
312.5
100.0
100.0
30-t
BLKH
40
40
100.0
100.0
-20
40
40
64fs
50
30+t
BLKL
70
70
20
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2) Microcomputer Interface Timing
(AVDD=DVDD,AVB,DVB=5.0V
±
5%,Ta=25
°
C;
master clock 16.9344MHz,XTI=384fs[fs=44.1kHz];CL=20pF)
Parameter
Symbol
t
CSW
t
RSW
t
WRC
t
WRS
t
WSC
t
SCW
t
SLK
t
SLKL
t
SLKH
t
SIH
t
SIS
t
CSHR
min
100
100
100
100
100
typ
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
From CS"
" to WRQ"
"
From RST"
" to WRQ"
"
From WRQ"
" to CS"
"
From WRQ"
" to RST"
"
From WRQ"
" to SCLK"
"
From Last SCLK"
" to WRQ"
"
SCLK cycle
SCLK pulse width Low
pulse width High
SI latch hold time
SI latch set Up time
From CS"
" to
cancellation of SO,WRDY "Hi-z" (note2)
From CS"
" to SO,WRDY"Hi-z" (note2)
From CS"
" to DRDY"
"
From SCLK"
" to SO setup time (note2)
note 1 : Master clock cycle
×
3
note 2 : See timing chart.
t
CSHS
t
CSDR
t
SOS
166(note1)
200
80
80
50
50
100
800
100
40
ns
ns
ns
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