參數(shù)資料
型號(hào): AK5702
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 4-Channel ADC with PLL & MIC-AMP
中文描述: 4通道ADC,帶鎖相環(huán)
文件頁(yè)數(shù): 46/76頁(yè)
文件大?。?/td> 933K
代理商: AK5702
[AK5702]
MS0623-E-00
2007/06
- 46 -
When writing to the IVA/BL7-0 and IVA/BR7-0 bits continuouslly, the control register should be written by an interval
more than zero crossing timeout. If not, IVA/BL and IVA/BR are not changed since zero crossing counter is reset at every
write operation. If the same register value as the previous write operation is written to IVA/BL and IVA/BR, this write
operation is ignored and zero crossing counter is not reset. Therefore, IVA/BL and IVA/BR can be written by an interval
less than zero crossing timeout.
ALCA/B bit
ALCA /B Status
Disable
Enable
Disable
IVA/BL7-0 bits
E1H(+30dB)
IVA/BR7-0 bits
C6H(+20dB)
Internal IVA/BL
E1H(+30dB)
E1(+30dB) --> F1(+36dB)
E1(+30dB)
Internal IVA/BR
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
C6H(+20dB)
(1)
(2)
Figure 44. IVOL value during 2ch ALC operation
(1)
The IVA/BL value becomes the start value if the IVA/BL and IVA/BR are different when the ALC starts. The wait
time from ALC bit = “1” to ALC operation start by IVA/BL7-0 bits is at most recovery time (WTMA/B2-0 bits) plus
zerocross timeout period (ZTMA/B1-0 bits).
(2)
Writing to IVA/BL and IVA/BR registers (18H and 19H) is ignored during ALC operation. After ALC is disabled,
the IVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALCA/B bit
should be set to “1” by an interval more than zero crossing timeout period after ALCA/B bit = “0”.
相關(guān)PDF資料
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