參數(shù)資料
型號(hào): AK5392-VS
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Enhanced Dual Bit 24Bit ADC
中文描述: 增強(qiáng)雙位24位模數(shù)轉(zhuǎn)換器
文件頁數(shù): 11/19頁
文件大?。?/td> 171K
代理商: AK5392-VS
ASAHI KASEI
[AK5392]
0188-E-01
1997/11
- 11 -
OPERATION OVERVIEW
System Clock Input
The external clocks which are required to operate the AK5392 are MCLK, LRCK(fs),SCLK. MCLK should be
synchronized with LRCK but the phase is free of care. MCLK can be either 256fs or 384fs by setting CMODE pin.
When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). Table 1 illustrates standard
audio word rates and corresponding frequencies used in the AK5392.
As the AK5392 includes the phase detect circuit for LRCK, the AK5392 is reset automatically when the
synchronization is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
MCLK
fs
256fs
384fs
SCLK(128fs)
32.0kHz
44.1kHz
48.0kHz
8.1920MHz
11.2896MHz
12.2880MHz
Table 1 . Examples of System Clock
12.2880MHz
16.9344MHz
18.4320MHz
4.0960MHz
5.6448MHz
6.1440MHz
Serial Data Interface
AK5392 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 2 ). The
data format is MSB-first, 2's complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE2
L
L
H
H
SMODE1
L
H
L
H
Table 2 . Serial I/F Format
Mode
LRCK
Slave Mode
Master Mode
I2S Slave Mode
I2S Master Mode
Lch=H, Rch=L
Lch=H, Rch=L
Lch=L, Rch=H
Lch=L, Rch=H
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