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參數(shù)資料
| 型號： | AK5386 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Single-ended 24-Bit 192kHz ツヒ ADC |
| 中文描述： | 單端24位ADC的192kHz的ツヒ |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 154K |
| 代理商： | AK5386 |
ASAHI KASEI
[AK5386]
MS0579-E-00
2006/12
- 13 -
Audio Interface Format
Two kinds of data formats can be chosen with the DIF pin (Table 4). In both modes, the serial data is in MSB first, 2’s
complement format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
DIF pin
SDTO
0
L
24bit, MSB justified
1
H
24bit, I
2
S Compatible
Table 4. Audio Interface Format
LRCK
H/L
L/H
SCLK
Figure
Figure 1
Figure 2
≥
48fs or 32fs
≥
48fs or 32fs
LRCK
SCLK(64fs)
SDTO(o)
0
23 22
1 2
4
0
20 21
24
31 0 1 2
23 22
0
1
0
23
22
20 21
31
23:MSB, 0:LSB
Lch Data
Rch Data
24
3 2
1
22 23
23
1
2
3
4
Figure 1. Mode 0 Timing
LRCK
SCLK(64fs)
SDTO(o)
0
23 22
1 2
4
0
25
21
24
0 1
2
23 22
0
1
0
22
25
21
24
3 2 1
22 23
23
1
2
3
4
3
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1 Timing
Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz (@fs=48kHz)
and scales with sampling rate (fs).
HPF is controlled by CKS2-0 pins (Table 3). If HPF setting (ON/OFF) is changed at operating, click noise occurs by
changing DC offset. It is recommended that HPF setting is changed at PDN pin = “L”.
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| AK5386VT | 制造商:AKM 制造商全稱:AKM 功能描述:Single-ended 24-Bit 192kHz ツヒ ADC |
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| AK5388 | 制造商:AKM 制造商全稱:AKM 功能描述:120dB 24-bit 192kHz 4-Channel ADC |
| AK5388_09 | 制造商:AKM 制造商全稱:AKM 功能描述:120dB 24-bit 192kHz 4-Channel ADC |
| AK5388A | 制造商:AKM 制造商全稱:AKM 功能描述:120dB 24-bit 192kHz 4-Channel ADC |
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