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參數(shù)資料
| 型號： | AK5386 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Single-ended 24-Bit 192kHz ツヒ ADC |
| 中文描述： | 單端24位ADC的192kHz的ツヒ |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 154K |
| 代理商： | AK5386 |
ASAHI KASEI
[AK5386]
MS0579-E-00
2006/12
- 12 -
OPERATION OVERVIEW
System Clock
MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with
MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system
clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF) and master/slave are selected by CKS2-0 pins as
shown in Table 3. When MCLK is 192fs, 384fs or 768fs, the sampling frequency does not support variable pitch.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5386 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5386 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
MCLK
fs
128fs
N/A
N/A
N/A
N/A
192fs
N/A
N/A
N/A
N/A
256fs
N/A
N/A
N/A
384fs
N/A
N/A
N/A
512fs
768fs
32kHz
44.1kHz
48kHz
96kHz
192kHz
16.384MHz
22.5792MHz
24.576MHz
N/A
N/A
24.576MHz
33.8688MHz
36.864MHz
N/A
N/A
24.576MHz
N/A
36.864MHz
N/A
24.576MHz
36.864MHz
Table 1. System Clock Example
Mode
Sampling Frequency
8kHz
≤
fs
≤
54kHz
8kHz
≤
fs
≤
48kHz
54kHz < fs
≤
108kHz
48kHz < fs
≤
96kHz
108kHz < fs
≤
216kHz
96kHz < fs
≤
192kHz
Table 2. Sampling Frequency Range
MCLK
512fs
768fs
256fs
384fs
128fs
192fs
Normal Speed
Double Speed
Quad Speed
CKS2 pin CKS1 pin
CKS0 pin
HPF
Master/Slave
MCLK
SCLK
L
L
L
ON
Slave
128/192fs (Quad Speed)
256/384fs (Double Speed)
512/768fs (Normal Speed)
128/192fs (Quad Speed)
256/384fs (Double Speed)
512/768fs (Normal Speed)
256fs (Double Speed)
512fs (Normal Speed)
128fs (Quad Speed)
192fs (Quad Speed)
384fs (Double Speed)
768fs (Normal Speed)
≥
48fs or 32fs
(Note 13)
L
L
H
OFF
Slave
≥
48fs or 32fs
(Note 13)
L
L
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
ON
ON
ON
ON
ON
ON
Master
Master
Master
Master
Master
Master
64fs
64fs
64fs
64fs
64fs
64fs
Table 3. Mode Select
Note 13. SDTO outputs 16bit data at SCLK=32fs.
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