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參數(shù)資料
| 型號(hào)： | AK5381VT |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 24Bit 96kHz ツヒ ADC |
| 中文描述： | ADC的24位96kHz的ツヒ |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 144K |
| 代理商： | AK5381VT |
ASAHI KASEI
[AK5381]
MS0200-E-02
2006/01
- 14 -
Power down
The AK5381 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. In the power-down mode, the VCOM are AGND level. An analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after
4129 cycles of LRCK clock in master mode or 4132 cycles of LRCK clock in slave mode. During initialization, the ADC
digital data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle in the data
corresponding to the input signals after the end of initialization (Settling approximately takes the group delay time).
Normal Operation
Internal
State
PDN
Power-down
Initialize
Normal Operation
(1)
Idle Noise
GD
GD
“0”data
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
(2)
(3)
(4)
“0”data
Idle Noise
Notes:
(1) 4132/fs in slave mode and 4129/fs in master mode.
(2) Digital output corresponding to analog input has the group delay (GD).
(3) A/D output is “0” data at the power-down state.
(4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5381 should be in the power-down state.
Figure 3. Power-down/up sequence example
System Reset
The AK5381 should be reset once by bringing PDN pin “L” after power-up. In slave mode, the internal timing starts
clocking by the rising edge (falling edge at mode 1) of LRCK after exiting from reset and power down state by MCLK.
The AK5381 is power down state until LRCK is input. In master mode, the internal timing starts when MCLK is input.
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| AK5383VS | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
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