參數(shù)資料
型號(hào)： AK5381VT
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 24Bit 96kHz ツヒ ADC
中文描述： ADC的24位96kHz的ツヒ
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 144K
代理商： AK5381VT
ASAHI KASEI
[AK5381]
MS0200-E-02
2006/01
- 12 -
OPERATION OVERVIEW
System Clock
MCLK (256fs/384fs/512fs), SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be
synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency
and the system clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF), the input level (CMOS or TTL)
and master/slave are selected by CKS2-0 pins as shown in Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5381 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5381 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
MCLK
fs
256fs
8.192MHz
11.2896MHz
12.288MHz
24.576MHz
384fs
512fs
768fs
32kHz
44.1kHz
48kHz
96kHz
12.288MHz
16.9344MHz
18.432MHz
36.864MHz
16.384MHz
22.5792MHz
24.576MHz
N/A
24.576MHz
33.8688MHz
36.864MHz
N/A
Table 1. System Clock Example
CKS2
CKS1
CKS0
Input Level
HPF
Master/Slave
MCLK
SCLK
L
L
L
CMOS
ON
Slave
256/384fs (
～
96kHz)
512/768fs (
～
48kHz)
256/384fs (
～
96kHz)
512/768fs (
～
48kHz)
256fs (
～
96kHz)
512fs (
～
48kHz)
256fs/384/512/768fs
(
～
48kHz)
Reserved
384fs (
～
96kHz)
768fs (
～
48kHz)
≥
48fs or 32fs
L
L
H
CMOS
OFF
Slave
≥
48fs or 32fs
L
L
H
H
L
H
CMOS
CMOS
ON
ON
Master
Master
64fs
64fs
H
L
L
TTL*
ON
Slave
≥
48fs or 32fs
H
H
H
L
H
H
H
L
H
CMOS
CMOS
ON
ON
Table 2. Mode Select
Master
Master
64fs
64fs
Note: SDTO outputs 16bit data at SCLK=32fs.
Note: The AK5381 does not support TTL interface at 96kHz.
Audio Interface Format
Two kinds of data formats can be chosen with the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
DIF pin
SDTO
0
L
24bit, MSB justified
1
H
24bit, I
2
S Compatible
Table 3. Audio Interface Format
LRCK
H/L
L/H
SCLK
Figure
Figure 1
Figure 2
≥
48fs or 32fs
≥
48fs or 32fs
相關(guān)PDF資料
PDF描述
AK5383 Circular Connector; No. of Contacts:8; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-8 RoHS Compliant: No
AK5383VF Enhanced Dual bit 96 kHz 24-bit ADC
AK5383VS Enhanced Dual bit 96 kHz 24-bit ADC
AK5385B 24Bit 192kHz ツヒ ADC
AK5385BVF 24Bit 192kHz ツヒ ADC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK5381VTP-E2 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:
AK5383 制造商:AKM 制造商全稱:AKM 功能描述:Enhanced Dual bit 96 kHz 24-bit ADC
AK5383VF 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.B FOR AK5383VF
AK5383VS 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:
AK5383VSP-E2 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:ENHANCED DUAL BIT DELTA SEGMA 24BIT 96KHZ ADC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*