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參數(shù)資料
| 型號(hào)： | AK5371VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | AB 5C 2#8 3#12 SKT WALL MT REC |
| 中文描述： | 2聲道的A / D轉(zhuǎn)換器的USB我/女 |
| 文件頁(yè)數(shù)： | 7/32頁(yè) |
| 文件大?。?/td> | 256K |
| 代理商： | AK5371VQ |
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7
MS0103-E-00
MS0103-E-00
ASAHI KASEI
[AK 5371]
2001/06
Digital DC Characteristics
Ta=0 - 70
°
C; VD=3.0 - 3.6V; DGND=0V Measurement under static state
All digital pins except DP, DN. Schmitt hysteresis level of RST pin and levels of all test pins will not be tested
.
Parameter
EPDI, EPEN, EPSEL, pin “H” level input voltage
EPDI, EPEN, EPSEL pin “L” level input voltage
RSTN pin “H” level voltage
RSTN pin “L” level voltage
CS, SK, EPAO, SUSN pin “H” level output
voltage IOH = 2mA
CS, SK, EPAO, SUSN pin “L” level output
voltage IOL = -2mA
Input Leakage Current
Symbol
VIH
VIL
VIHR
VILR
VOH
Min
70%VD
T yp
Max
Units
V
V
V
V
V
30%VD
2.0
0.8
2.4
VOL
0.6
V
Iin
±
10
μ
A
Switching Characteristics
Ta=25
°
C, VA=VD=3.3V
Parameter
Master Clock Frequency
Reset input width @RSTN pin(low active)
DP,DN Single Ended Receiver Threshold
for H level
for L level
Time Width for USB Reset Signal Recognition*1
DP<VseL & DN< VseL to USB Reset mode
Device Ready Time from USB Reset
Ready for transaction after reset
Time Width for Suspend Recognition
Idle state ( DP > VseL & DN < VseL )
to Suspend mode
Resume Time from Suspend
First flip of DP/DN from Idle sate
To Device Ready*)
Device Ready: VREF, X’tal oscillator, and PLL get stable and bus transaction with normal rate is ready.
Symbol
MCLK
Wrst
Min
-
1.0
T yp
11.2896
Max
-
Units
MHz
us
VseH
VseL
2.0
0.8
V
Trst_rec
2.7
μ
s
Tdrr
10
ms
Tsus_rec
3.0
ms
Tresm
30
ms
Reset Mode
PLL
Clock
DN
DP
VD
Device
Connected
RSTN
Tdrr
min 20ms
Resume
min 10ms
resume time
resume recovery time
Trst_rec
Figure 1. Mode change with respect to BUS States 1 (Power on and device connected)
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