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參數(shù)資料
| 型號： | AK5371VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | AB 5C 2#8 3#12 SKT WALL MT REC |
| 中文描述： | 2聲道的A / D轉(zhuǎn)換器的USB我/女 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 256K |
| 代理商： | AK5371VQ |
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14
MS0103-E-00
MS0103-E-00
ASAHI KASEI
[AK 5371]
2001/06
System Block Diagram
The following figure shows the system connection diagram. This is an example which uses external 1K bit EEPROM (AK93C45A)
as Device and String Descriptor. If EEPROM is not used, EPEN pin should be tied to DGND.
Ceramic capacitors (0.1uF) for VA pin, VD pin, VREF pin and VCOM pin should be located as near as possible.
RSTN
XTALIN
MICBIAS
MICR
AMPR1O
AMPR2I
AMP2RO
AMP2O
VREF
Testmode 1
Testmode 2
Testmode 3
DP
DN
1.5k
D+
D-
To Host/Hub
11.2896M
15p
C3:1000p
C1:1.0u<
100
u
0.1u
0.1u
4.7u
0.1u
4.7u
Regulator
0.1u
10u
10uH
3300p
56k
0.1u
51k
0.1u
4.7u
0.1u
4.7u
Test
VCOM
VA AGND
VD DGND
BGND
XTALOUT
15p
18k
8200p
6800p
LFLT1,2
C2:0.33u
MICL
AMPL1O
AMPL2I
C1:1.0u<
C2:0.33u
C3:1000p
<REMARK> This drawing does NOT mean physical pin locations/ordering
Phone J ack
STEREO SW
C1 is specified for lower end cut-off frequency
C3 forms Anti-aliasing filter in conjuction with the
internal resistor at AMPR2O/AMPL2O
R0: 0
resister when BIASSEL is Low
300
(TBD) resister when BIASSEL is High
R1:4.7k
100
u
0.1u
R1:4.7k
10
GND
analog
GND
5V
GND
digital
GND
10u
CS
SK
EPAO
EPDI
EEPROM
R0
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