參數(shù)資料
型號(hào): AK5365VQ
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl
中文描述: 24位96kHz與SELETOR藝術(shù)發(fā)展局/美國(guó)PGA /淋巴瘤
文件頁(yè)數(shù): 10/41頁(yè)
文件大小: 286K
代理商: AK5365VQ
ASAHI KASEI
[AK5365
]
MS0164-E-01
2002/08
- 10 -
Parameter
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
” to CCLK “
CCLK “
” to CSN “
Control Interface Timing (I
2
C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 17)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
-
4.7
4.0
4.7
4.0
4.7
0
0.25
-
-
4.0
0
100
-
-
-
-
-
-
-
1.0
0.3
-
50
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
Reset Timing
PDN Pulse Width (Note 18)
PDN “
” to SDTO valid (Note 19)
PWN “
” to SDTO valid (Note 20)
tPD
tPDV
tPDV
150
516
516
ns
1/fs
1/fs
Note 17. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 18. The AK5365 can be reset by bringing the PDN pin = “L”.
Note 19. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Note 20. This cycle is the number of LRCK rising edges from the PWN bit = “1”.
Purchase of Asahi Kasei Microsystems Co., Ltd I
2
C components conveys a license under the Philips I
2
C
patent to use the components in the I
C system, provided the system conform to the I
C specifications
defined by Philips.
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