參數(shù)資料
型號： AK5365
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl
中文描述： 24位96kHz與SELETOR藝術(shù)發(fā)展局/美國PGA /淋巴瘤
文件頁數(shù)： 36/41頁
文件大?。?/td> 286K
代理商： AK5365
ASAHI KASEI
[AK5365
]
MS0164-E-01
2002/08
- 36 -
Addr
06H
Register Name
ALC Mode Control 1
Default
D7
0
0
D6
0
0
D5
D4
ALC
0
D3
FR
1
D2
D1
D0
ZELMN
1
LMTH
0
RATT
0
LMAT
0
LMAT: ALC Limiter ATT step (see Table 18)
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level set by LMTH
bit, the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value
is 94H and the LMAT bit = “1”, the IPGA transition to 92H when the ALC limiter operation starts, resulting in the
input signal level being attenuated by 1dB (=0.5dB x 2).
LMAT
0
1
Table 18. ALC limiter ATT step
ATT Step
1
2
Default
RATT: ALC Recovery gain step (see Table 19)
During the ALC recovery operation, the number of steps changed from the current IPGA value is set. For example,
when the current IPGA value is 82H and RATT bit = “1” is set, the IPGA changes to 84H by the ALC recovery
operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the
reference level (REF7-0 bits), the IPGA value does not increase.
RATT
0
1
Table 19. ALC recovery gain step
Gain Step
1
2
Default
LMTH: ALC Limiter detection level / Recovery waiting counter reset level (see Table 20)
The ALC limiter detection level and the ALC recovery counter reset level may be offset by about
±
2dB.
LMTH
0
1
ALC Limiter Detection Level
ALC Output
≥
0.5dBFS
ALC Output
≥
2.0dBFS
Table 20. ALC Limiter detection level / Recovery waiting counter reset level
ALC Recovery Waiting Counter Reset Level
0.5dBFS
>
ALC Output
≥
2.5dBFS
2.0dBFS
>
ALC Output
≥
4.0dBFS
Default
FR: ALC fast recovery
0 : Disable
1 : Enable (Default)
When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation.
ALC:
ALC enable flag
0 : ALC Disable (Default)
1 : ALC Enable
ZELMN: Zero crossing enable flag at ALC limiter operation
0 : Enable
1 : Disable (Default)
When the ZELMN bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently. The
zero crossing timeout is the same as the ALC recovery operation. When the ZELMN bit = “1”, the IPGA value is
changed immediately. The ALC Limiter period can be set up by a ZTM 1-0 bits when ZELMN bit = “0”, it can be
set up by a LTM1-0 bits when ZELMN bit = “1”
相關(guān)PDF資料
PDF描述
AK5365VQ 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl
AK5366VR 24-Bit 48kHz ツヒ ADC with Selector/PGA/ALC
AK5366 Circular Connector; No. of Contacts:6; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-6 RoHS Compliant: No
AK5366VQ Circular Connector; No. of Contacts:6; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-6 RoHS Compliant: No
AK5370 Circular Connector; No. of Contacts:6; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-6 RoHS Compliant: No
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