參數(shù)資料
型號： AK5365
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl
中文描述： 24位96kHz與SELETOR藝術發(fā)展局/美國PGA /淋巴瘤
文件頁數(shù)： 14/41頁
文件大?。?/td> 286K
代理商： AK5365
ASAHI KASEI
[AK5365
]
MS0164-E-01
2002/08
- 14 -
OPERATION OVERVIEW
System Clock
MCLK (256fs/384fs/512fs), BICK (48fs
～
) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical. MCLK frequency is automatically detected in slave mode.
Table 1 shows the relationship of typical sampling frequency and the system clock frequency.
MCLK (256fs/384fs/512fs) is required in master mode. MCLK frequency is selected by CKS1-0 bits as shown in Table 2.
In master mode, after setting CKS1-0 bits, there is a possibility the frequency and duty of LRCK and BICK outputs become
an abnormal state.
All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L” and PWN bit = “1”. If these clocks
are not provided, the AK5365 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5365 in power-down mode (PDN pin = “L” or PWN bit = “0”). In master mode, the
master clock (MCLK) must be provided unless PDN pin = “L”.
MCLK
384fs
12.288MHz
16.9344MHz
18.432MHz
N/A
fs
256fs
8.192MHz
11.2896MHz
12.288MHz
24.576MHz
Table 1. System clock example (Slave mode)
512fs
32kHz
44.1kHz
48kHz
96kHz
16.384MHz
22.5792MHz
24.576MHz
N/A
MCLK
CKS1
CKS0
32kHz
≤
fs
≤
48kHz
256fs
512fs
384fs
N/A
48kHz
<
fs
≤
96kHz
256fs
N/A
N/A
N/A
0
0
1
1
0
1
0
1
Default
Table 2. Master clock frequency select (Master mode)
Audio Interface Format
Two kinds of data formats can be chosen with the DIF bit (Table 3) and the CTRL pin (Table 4). The DIF bit and CTRL pin
are ORed between pin and register. In both modes, the serial data is in MSB first, 2’s compliment format. The SDTO is
clocked out on the falling edge of BICK. The audio interface supports both master and slave modes. In master mode, BICK
and LRCK are output with the BICK frequency fixed to 64fs and the LRCK frequency fixed to 1fs.
Mode
0
1
DIF bit
0
1
SDTO
LRCK
H/L
L/H
BICK
≥
48fs
≥
48fs
Figure
Figure 1
Figure 2
24bit, MSB justified
24bit, I
2
S Compatible
Table 3. Audio Interface Format (CTRL pin = “L”)
Default
Mode
0
1
CTRL pin
L
H
SDTO
LRCK
H/L
L/H
BICK
≥
48fs
≥
48fs
Figure
Figure 1
Figure 2
24bit, MSB justified
24bit, I
2
S Compatible
Table 4. Audio Interface Format (DIF bit = “0”)
相關PDF資料
PDF描述
AK5365VQ 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl
AK5366VR 24-Bit 48kHz ツヒ ADC with Selector/PGA/ALC
AK5366 Circular Connector; No. of Contacts:6; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-6 RoHS Compliant: No
AK5366VQ Circular Connector; No. of Contacts:6; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-6 RoHS Compliant: No
AK5370 Circular Connector; No. of Contacts:6; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-6 RoHS Compliant: No
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