參數(shù)資料
型號(hào)： AK5359VT
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 24-Bit 192kHz ツヒ ADC
中文描述： 24位192kHz的ツヒ模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 10/18頁(yè)
文件大?。?/td> 145K
代理商： AK5359VT
ASAHI KASEI
[AK5359]
MS0428-E-00
2005/09
- 10 -
OPERATION OVERVIEW
System Clock
MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with
MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system
clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF) and master/slave are selected by CKS2-0 pins as
shown in Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5359 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5359 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
MCLK
fs
128fs
N/A
N/A
N/A
N/A
192fs
N/A
N/A
N/A
N/A
256fs
8.192MHz
11.2896MHz
12.288MHz
24.576MHz
N/A
Table 1. System Clock Example
384fs
512fs
768fs
32kHz
44.1kHz
48kHz
96kHz
192kHz
12.288MHz
16.9344MHz
18.432MHz
36.864MHz
N/A
16.384MHz
22.5792MHz
24.576MHz
N/A
N/A
24.576MHz
33.8688MHz
36.864MHz
N/A
N/A
24.576MHz
36.864MHz
CKS2
CKS1
CKS0
HPF
Master/Slave
MCLK
SCLK
L
L
L
ON
Slave
128/192fs (108k<fs
≤
216k)
256/384fs (8k
≤
fs
≤
108k)
512/768fs (8k
≤
fs
≤
54k)
128/192fs (108k<fs
≤
216k)
256/384fs (8k
≤
fs
≤
108k)
512/768fs (8k
≤
fs
≤
54k)
256fs (8k
≤
fs
≤
108k)
512fs (8k
≤
fs
≤
54k)
128fs (108k<fs
≤
216k)
192fs (108k<fs
≤
216k)
384fs (8k
≤
fs
≤
108k)
768fs (8k
≤
fs
≤
54k)
≥
48fs or 32fs
L
L
H
OFF
Slave
≥
48fs or 32fs
L
L
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
ON
ON
ON
ON
ON
ON
Master
Master
Master
Master
Master
Master
Table 2. Mode Select
64fs
64fs
64fs
64fs
64fs
64fs
Note: SDTO outputs 16bit data at SCLK=32fs.
Audio Interface Format
Two kinds of data formats can be chosen with the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
DIF pin
SDTO
0
L
24bit, MSB justified
1
H
24bit, I
2
S Compatible
Table 3. Audio Interface Format
LRCK
H/L
L/H
SCLK
Figure
Figure 1
Figure 2
≥
48fs or 32fs
≥
48fs or 32fs
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