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參數(shù)資料
| 型號(hào)： | AK5352 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 96kHz Sampling ΔΣ 20bit ADC(用于DAT和DVD的20位2通道A/D轉(zhuǎn)換器（采用加強(qiáng)型雙位結(jié)構(gòu)）) |
| 中文描述： | 96kHz采樣ΔΣ20位模數(shù)轉(zhuǎn)換器（用于逸和影碟的20位2通道的A / D轉(zhuǎn)換器（采用加強(qiáng)型雙位結(jié)構(gòu)）） |
| 文件頁(yè)數(shù)： | 9/19頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | AK5352 |
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ASAHI KASEI
[AK5352]
0155-E-00
1997/1
- 9 -
SWITCHING CHARACTERISTICS
(Ta=25
°
C
; VA,VD,VB=5.0V
±
5%; C
L
=20pF)
Parameter
Symbol
min
typ
max
Unit
Control Clock Frequency
Master Clock 256fs: (fs =
～
98kHz)
Pulse width Low
Pulse width High
384fs: (fs =
～
54kHz)
Pulse width Low
Pulse width High
Serial Data Output Clock
Channel Select Clock(Sampling Frequency)
Duty Cycle
Serial Interface Timing
Slave Mode(SMODE1="L")
SCLK Period
SCLK Pulse width Low
Pulse width High
SCLK Rising to LRCK Edge (Note 19 )
LRCK Edge to SCLK Rising (Note 19 )
LRCK Edge to SDATA MSB Valid
SCLK Falling to SDATA Valid
SCLK Rising to FSYNC Edge (Note 19 )
FSYNC Edge to SCLK Rising (Note 19 )
Master Mode(SMODE1="H")
SCLK Frequency
Duty Cycle
FSYNC Frequency
Duty Cycle
SCLK Falling to LRCK Edge
LRCK Edge to FSYNC Rising
SCLK Falling to SDATA Valid
SCLK Falling to FSYNC Edge
Power down timing
PD
Pulse width
PD
Rising to SDATA Valid (Note 20 )
Note 18 : Refer to Serial Data Interface.
Note 19 : Specified LRCK and FSYNC edges not to coincide with the rising edges of SCLK.
Note 20 : The number of LRCK rising edges after PD brought high. The value is in master mode.
In slave mode it becomes one LRCK clock(1/fs) longer.
f
CLK
t
CLKL
t
CLKH
f
CLK
t
CLKL
t
CLKH
f
SLK
f
s
4.096
15.9
15.9
6.144
20.83
20.83
16
25
12.288
18.432
3.072
48
25.088
20.736
6.144
98
75
MHz
ns
ns
MHz
ns
ns
MHz
kHz
%
(Note 18 )
t
SLK
t
SLKL
t
SLKH
t
SLR
t
LRS
t
DLR
t
DSS
t
SF
t
FS
f
SLK
f
FSYNC
t
SLR
t
LRF
t
DSS
t
SF
159.4
65
65
30
30
30
30
-20
-20
64fs
50
2fs
50
1
50
50
20
50
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
Hz
%
ns
tslk
ns
ns
t
PDW
t
PDV
150
516
ns
1/fs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK5352-VF | 96kHz Sampling 20bit ADC |
| AK5353 | 96kHz ΔΣ 24bit ADC with Single-ended Input(帶寬采樣率4KHz到96KHz和單端輸入的24位立體聲ΔΣA/D轉(zhuǎn)換器) |
| AK5353VT | 96kHz 24BIT ADC WITH SIGLE-ENDED INPUT |
| AK5354 | Lowe Power 20Bit ΔΣ ADC with PGA(帶可編程增益放大器的低電壓20位ΔΣA/D轉(zhuǎn)換器) |
| AK5354VT | Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK5352VF | 功能描述:IC ADC 20BIT SAMPLING 24VSOP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購(gòu)買時(shí)間 標(biāo)準(zhǔn)包裝:1,000 |
| AK5352-VF | 制造商:AKM 制造商全稱:AKM 功能描述:96kHz Sampling 20bit ADC |
| AK5353 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.B FOR AK5353 |
| AK5353VT | 制造商:AKM 制造商全稱:AKM 功能描述:96kHz 24BIT ADC WITH SIGLE-ENDED INPUT |
| AK5353VTP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:24BIT 96K 96DB |
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