參數(shù)資料
型號(hào)： AK5352
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 96kHz Sampling ΔΣ 20bit ADC(用于DAT和DVD的20位2通道A/D轉(zhuǎn)換器（采用加強(qiáng)型雙位結(jié)構(gòu)）)
中文描述： 96kHz采樣ΔΣ20位模數(shù)轉(zhuǎn)換器（用于逸和影碟的20位2通道的A / D轉(zhuǎn)換器（采用加強(qiáng)型雙位結(jié)構(gòu)））
文件頁(yè)數(shù)： 12/19頁(yè)
文件大?。?/td> 174K
代理商： AK5352
ASAHI KASEI
[AK5352]
0155-E-00
1997/1
- 12 -
Serial Data Interface
Audio Serial Interface has four kinds of mode, it can be changed by SMODE1 and SMODE2 pins. Data format
is MSB first, 2's complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE1
L
H
L
H
SMODE2
L
L
H
H
Mode
L/R polarity
Lch=H, Rch=L
Lch=H, Rch=L
Lch=L, Rch=H
Lch=L, Rch=H
Slave Mode: 20bit, MSB justified
Master Mode: Similar to I
Slave Mode: I
Master Mode: I
Table 2 . Serial Interface
2
S
2
S
2
S
1) SLAVE mode
An output channel is defined by LRCK. Both channel data are output in sequence, in order of the Lch first then
Rch at the rate of fs. Data bits are clocked out via the SDATA pin at SCLK rate. Figure 1 and Figure 3 shows
data output timing at SCLK=64fs. FSYNC enables SCLK to start clocking out data. The MSB is clocked out by
the LRCK edge. SCLK causes the ADC to output succeeding bits when FSYNC is high. However, as I
mode ignores FSYNC, it should hold "L" or "H".
2
S slave
2) MASTER mode
In MASTER mode, the A/D converter is driven from a master clock(MCLK:256fs/384fs) and outputs all other
clocks(LRCK, SCLK). The falling edge of SCLK causes the ADC to output each bit. Figure 2 and Figure 4
shows the output timing. 2x fs clock of 50% duty is output via the FSYNC pin. FSYNC rises one SCLK cycle
after the transition of LRCK edges and stays high during 16 serial clocks(16*t
SLK
). Upper 16 bit data is output
during FSYNC "H", lower 4 bit is output after FSYNC "L" transition.
Figure 1 . Data Output Timing (Slave mode)
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PDF描述
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