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參數(shù)資料
| 型號： | AK5351-VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:26; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-26 RoHS Compliant: No |
| 中文描述： | 增強雙位20位模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 174K |
| 代理商： | AK5351-VF |
ASAHI KASEI
[AK5351]
0166-E-00
1997/4
- 11 -
Serial Data Interface
Audio Serial Interface has four kinds of mode, it can be changed by SMODE1 and SMODE2 pins. Data format
is MSB first, 2's complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE1
L
H
L
H
SMODE2
L
L
H
H
Mode
L/R polarity
Lch=H, Rch=L
Lch=H, Rch=L
Lch=L, Rch=H
Lch=L, Rch=H
Slave Mode: 20bit, MSB justified
Master Mode: Similar to I
Slave Mode: I
Master Mode: I
Table 2 . Serial Interface
2
S
2
S
2
S
1) SLAVE mode
An output channel is defined by LRCK. Both channel data are output in sequence, in order of the Lch first then
Rch at the rate of fs. Data bits are clocked out via the SDATA pin at SCLK rate. Figure 1 and Figure 3 shows
data output timing at SCLK=64fs. FSYNC enables SCLK to start clocking out data. The MSB is clocked out by
the LRCK edge. SCLK causes the ADC to output succeeding bits when FSYNC is high. However, as I
mode ignores FSYNC, it should hold "L" or "H".
2
S slave
2) MASTER mode
In MASTER mode, the A/D converter is driven from a master clock(MCLK:256fs/384fs) and outputs all other
clocks(LRCK, SCLK). The falling edge of SCLK causes the ADC to output each bit. Figure 2 and Figure 4
shows the output timing. 2x fs clock of 50% duty is output via the FSYNC pin. FSYNC rises one SCLK cycle
after the transition of LRCK edges and stays high during 16 serial clocks(16*t
SLK
). Upper 16 bit data is output
during FSYNC "H", lower 4 bit is output after FSYNC "L" transition.
Figure 1 . Data Output Timing (Slave mode)
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| AK5353 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.B FOR AK5353 |
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