參數(shù)資料
型號: AK4651
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16Bit ツヒ CODEC with MIC/HP/SPK-AMP
中文描述: 16位ツヒ編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 41/66頁
文件大?。?/td> 605K
代理商: AK4651
ASAHI KASEI
[AK4651]
MS0503-E-00
2006/04
- 41 -
ALC2 Operation
Input resistance of the ALC2 (MIN pin) is 24k
(typ) and centered around VCOM voltage. Figure 29 shows input-output
relationship at ALC2 operation (0dBV=1Vrms =2.828Vpp).
The limiter detection level is proportional to HVDD. The output level is limited by the ALC2 circuit when the
Speaker-amp output level exceeds +1.8dBV@HVDD=3.3V. When a continuous signal of +1.8dBV or greater is input to
the ALC2 circuit, the output level is attenuated by ALC2 operation. The change period of the ALC2 limiter operation is
set by the ROTM bit and the attenuation level is 0.5dB/step (Table 39).
When the Speaker-amp output level is equal to or lower than
2dBV@HVDD=3.3V, the ALC2 recovery opeation starts.
The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the
output level of the Speaker-amp goes to
2dBV@HVDD=3.3V. The ALC2 maximum gain is +18dB. The ROTM bit sets
the ALC2 recovery operation period (Table 39).
When the output signal is between +1.8dBV and
2dBV, the ALC2 limiter or recovery operations are not done.
When the PMSPK bit changes from “0” to “1”, the initilization cycle (2048/fs = 46.4ms @fs=44.1kHz at ROTM bit =
“0”, 512/fs = 11.6ms @fs=44.1kHz at the ROTM bit = “1”) starts. This fs value is set by Addr=32H (ADC sampling
frequence). The ALC2 is disabled during the initilization cycle and the ALC2 starts after completing the initilization
cycle.
Parameter
ALC2 Limiter operation
Operation Start Level
+1.8dBV
ROTM bit = “0”
2/fs = 45
μ
s@fs=44.1kHz
Period
ROTM bit = “1”
2/fs = 181
μ
s@fs=11.025kHz
Zero-crossing Detection
Diabled
ATT/GAIN
0.5dB step
Table 39. Limiter /Recovery of ALC2 at HVDD=3.3V
SPK Out
ALC2 Recovery operation
2dBV
2048/fs = 46.4ms@fs=44.1kHz
512/fs = 46.4ms@fs=11.025kHz
Enabled (Timeout = 2048/fs)
1dB step
DAC In
+1.8dBV
0.2dBV
2
2
2
0
+3.8dBV
(ALC2=OFF)
(Limitter)
(Recovery)
18.2dBV
Figure 29. DAC input – Speaker output relationship (HVDD=3.3V, ALC2 bit = “1”)
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