參數(shù)資料
型號: AK4648
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: Stereo CODEC with MIC/HP/SPK-AMP
中文描述: 立體聲編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 53/119頁
文件大?。?/td> 1272K
代理商: AK4648
[AK4648]
MS0625-E-01
2007/06
- 53 -
3.
Example of ALC Operation
Table 34 shows the examples of the ALC setting for MIC recording.
fs=8kHz
Operation
4.1dBFS
Enable
32ms
fs=44.1kHz
Operation
4.1dBFS
Enable
23.2ms
Register Name
Comment
Data
01
0
01
Data
01
0
11
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
longer data as ZTM1-0 bits.
Maximum gain at recovery operation
WTM2-0
001
32ms
011
23.2ms
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
E1H
+30dB
E1H
+30dB
Gain of IVOL
E1H
+30dB
E1H
+30dB
Limiter ATT step
Recovery GAIN step
Fast Recovery Speed
ALC enable
00
00
00
1
1 step
1 step
4 times
Enable
00
00
00
1
1 step
1 step
4 times
Enable
Table 34. Example of the ALC setting
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.
LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN and RFST1-0 bits
Manual Mode
* The value of IVOL should be
the same or smaller than REF’s
WR (ZTM1-0, WTM2-0, RFST1-0)
WR (REF7-0)
WR (IVL/R7-0)
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Zero Crossing Timeout Period = 32ms@8kHz
Limiter and Recovery Step = 1
Fast Recovery Speed = 4 step
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level =
4.1dBFS
ALC bit = “1”
(1) Addr=06H, Data=14H
(2) Addr=08H, Data=E1H
(5) Addr=07H, Data=21H
(3) Addr=09H&0CH, Data=E1H
ALC Operation
Note : WR : Write
WR (RGAIN1, LMTH1)
(4) Addr=0BH, Data=00H
Figure 35. Registers set-up sequence at ALC operation
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