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參數(shù)資料
| 型號： | AK4628VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | HIGH PERFORMANCE MULTI CHANNEL AUDIO CODEC |
| 中文描述： | 高性能多通道音頻解碼器 |
| 文件頁數(shù)： | 30/41頁 |
| 文件大?。?/td> | 546K |
| 代理商： | AK4628VQ |
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ASAHI KASEI
[AK4628]
MS0211-E-02
2004/03
- 30 -
(2) I
2
C-bus Control Mode (I2C= “H”)
AK4628 supports the standard-mode I
2
C-bus (max:100kHz). Then AK4628 does not support a fast-mode I
2
C-bus
system (max:400kHz). The CSN pin should be connected to DVDD at the I
C-bus mode.
Figure 17 shows the data transfer sequence at the I
2
C-bus mode. All commands are preceded by a START condition.
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 22). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data
direction bit (R/W) (Figure 19). The most significant five bits of the slave address are fixed as “00100”. The next
two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The
hard-wired input pins (CAD1 pin and CAD0 pin) set them. If the slave address match that of the AK4628 and R/W
bit is “0”, the AK4628 generates the acknowledge and the write operation is executed. If R/W bit is “1”, the AK4628
generates the not acknowledge since the AK4628 can be only a slave-receiver. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 23).
The second byte consists of the address for control registers of the AK4628. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 20). Those data after the second byte contain control data. The format is
MSB first, 8bits (Figure 21). The AK4628 generates an acknowledge after each byte has been received. A data
transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA
line while SCL is HIGH defines a STOP condition (Figure 22).
The AK4628 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4628 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte
instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal
5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address
exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data
will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 24) except for the START and the STOP
condition.
S
T
A
R
T
Slave
Address
Address(n)
SDA
A
C
K
A
C
K
S
A
C
K
Sub
Data(n)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W
A
C
K
Figure 18. Data transfer sequence at the I
2
C-bus mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 19. The first byte
*
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 20. The second byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 21. Byte structure after the second byte
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4631 | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4632 | 16-Bit ツヒ Mono CODEC with ALC & MIC/SPK/Video-AMP |
| AK4632VN | 16-Bit ツヒ Mono CODEC with ALC & MIC/SPK/Video-AMP |
| AK4633VN | 16bit mono CODEC with MIC/SPK amplifier. |
| AK4633 | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4629 | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance Multi-channel Audio CODEC |
| AK4629VQ | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance Multi-channel Audio CODEC |
| AK4631 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4631_1 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Mono CODEC with ALC & MIC/SPK-AMP |
| AK4631VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Mono CODEC with ALC & MIC/SPK-AMP |
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