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參數(shù)資料
| 型號： | AK4628VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | HIGH PERFORMANCE MULTI CHANNEL AUDIO CODEC |
| 中文描述： | 高性能多通道音頻解碼器 |
| 文件頁數(shù)： | 16/41頁 |
| 文件大小： | 546K |
| 代理商： | AK4628VQ |
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ASAHI KASEI
[AK4628]
MS0211-E-02
2004/03
- 16 -
OPERATION OVERVIEW
System Clock
The external clocks, which are required to operate the AK4628, are MCLK, LRCK and BICK. MCLK should be
synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS = “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each
sampling speed is set automatically. (Table 2, 3, 4). In Auto Setting Mode (ACKS = “1”), as MCLK frequency is detected
automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to
set DFS.
External clocks (MCLK, BICK) should always be present whenever the AK4628 is in normal operation mode (PDN =
“H”). If these clocks are not provided, the AK4628 may draw excess current because the device utilizes dynamic
refreshed logic internally. If the external clocks are not present, the AK4628 should be in the power-down mode (PDN =
“L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4628 is in the power-down mode until
MCLK and LRCK are input.
DFS1
DFS0
Sampling Speed (fs)
0
0
Normal Speed Mode
0
1
Double Speed Mode
1
0
Quad Speed Mode
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
MCLK (MHz)
fs
256fs
384fs
32.0kHz
8.1920
12.2880
44.1kHz
11.2896
16.9344
48.0kHz
12.2880
18.4320
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
MCLK (MHz)
fs
128fs
192fs
88.2kHz
11.2896
16.9344
96.0kHz
12.2880
18.4320
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
(Note: At Double speed mode(DFS1= “0”, DFS0 = “1”), 128fs and 192fs are not available for ADC.)
LRCK
MCLK (MHz)
fs
128fs
192fs
176.4kHz
22.5792
-
192.0kHz
24.5760
-
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
(Note: At Quad speed mode(DFS1= “1”, DFS0 = “0”) are not available for ADC.)
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
Default
BICK (MHz)
64fs
2.0480
2.8224
3.0720
512fs
16.3840
22.5792
24.5760
BICK (MHz)
64fs
5.6448
6.1440
256fs
22.5792
24.5760
BICK (MHz)
64fs
11.2896
12.2880
256fs
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相關(guān)PDF資料 |
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|---|---|
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| AK4633VN | 16bit mono CODEC with MIC/SPK amplifier. |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4629 | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance Multi-channel Audio CODEC |
| AK4629VQ | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance Multi-channel Audio CODEC |
| AK4631 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4631_1 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Mono CODEC with ALC & MIC/SPK-AMP |
| AK4631VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Mono CODEC with ALC & MIC/SPK-AMP |
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