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參數(shù)資料
| 型號： | AK4626A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | High Performance Multi-channel Audio CODEC |
| 中文描述： | 高性能多通道音頻解碼器 |
| 文件頁數(shù)： | 27/40頁 |
| 文件大?。?/td> | 573K |
| 代理商： | AK4626A |
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ASAHI KASEI
[AK4626A]
MS0397-E-00
2005/06
- 27 -
Reset Function
When RSTN = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go
to VCOM voltage, DZF1-2 pins go to “H” and SDTO pin goes to “L”. Because some click noise occurs, the analog output
should muted externally if the click noise influences system application. Figure 15 shows the power-up sequence.
ADC Internal
State
RSTN bit
Normal Operation
Digital Block Power-down
Normal Operation
Don’t care
GD
GD
Clock In
MCLK,LRCK,SCLK
ADC In
(Analog)
“0”data
ADC Out
(Digital)
Normal Operation
Normal Operation
DAC Internal
State
“0”data
DAC In
(Digital)
DAC Out
(Analog)
GD
GD
(2)
(2)
(3)
(4)
(6)
(6)
DZF1/DZF2
(7)
Internal
RSTN bit
Digital Block Power-down
1~2/fs (9)
4~5/fs (9)
4
～
5/fs (8)
(5)
516/fs
Init Cycle
(1)
Notes:
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
noise influences system application.
(5) The analog outputs go to VCOM voltage.
(6) Click noise occurs at 4
～
5/fs after RSTN bit becomes “0”, and occurs at 1
～
2/fs after RSTN bit becomes “1”. This
noise is output even if “0” data is input.
(7) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode. When exiting the reset mode, “1”
should be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed.
(8) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 6~7/fs after RSTN bit becomes “1”.
(9) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
Figure 15. Reset sequence example
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4626AVQ | High Performance Multi-channel Audio CODEC |
| AK4628A | High Performance Multi-channel Audio CODEC |
| AK4628AVQ | High Performance Multi-channel Audio CODEC |
| AK4628 | HIGH PERFORMANCE MULTI CHANNEL AUDIO CODEC |
| AK4628VQ | HIGH PERFORMANCE MULTI CHANNEL AUDIO CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4626AVQ | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance Multi-channel Audio CODEC |
| AK4627 | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance Multi-channel Audio CODEC |
| AK4627VQ | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance Multi-channel Audio CODEC |
| AK4628 | 制造商:AKM 制造商全稱:AKM 功能描述:HIGH PERFORMANCE MULTI CHANNEL AUDIO CODEC |
| AK4628A | 制造商:AKM 制造商全稱:AKM 功能描述:single chip CODEC that includes two channels of ADC and eight channels of DAC. |
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