參數(shù)資料
型號: AK4620BVF
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 24-Bit 192kHz Audio CODEC with IPGA
中文描述: 24位192kHz的音頻編解碼器與單親遺傳算法
文件頁數(shù): 24/42頁
文件大?。?/td> 410K
代理商: AK4620BVF
ASAHI KASEI
[AK4620B]
MS0401-E-00
2005/07
- 24 -
Overflow Detection
The ADC has a channel independent overflow detection function. This function is enabled in the parallel control mode, or
when the ZOS bit = ZOE bit = “0”in serial control mode. OVFL/R pins go to “H” if each Lch/Rch analog input overflows
(exceeds -0.3dBFS). The output of each OVFL/R pin has same group delay as ADC against analog input. OVFL/R pin is
“L” for 516/fs (=10.8ms @fs=48kHz) after PDN pin = “
”, and then overflow detection is enabled.
Zero detection
The DAC has a channel-independent zero detect function. The zero detect function is enabled when the ZOS bit = “1” and
the ZOE bit = “0”in serial control mode. When the input data at both channels is continuously zero for 8192 LRCK cycles,
the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately goes to “L” if the input data of each
channel is not zero after DZF “H”. If the RSTDA bit is “0”, the DZF pins of both channels go to “H”. DZF pins of both
channels go to “L” at 4~5/fs after the RSTDA bit becomes “1”. Zero detect function can be disabled by the ZOE bit. In
this case, the DZF pins of both channels are always “L”. The DZFB bit can invert the polarity of the DZF pin.
Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz at
fs=44.1kHz. The digital high pass filter cutoff frequency scales with the sampling rate (fs). In parallel mode, the HPF is
always enabled. In serial mode, the HPF can control each channel by HPLN/HPRN bits.
De-emphasis Filter
The DAC includes a digital de-emphasis filter (tc=50/15
μ
s) via an integrated IIR filter. This filter corresponds to three
frequencies (32kHz, 44.1kHz, 48kHz). This setting is done via control register (DEM1-0 bits). This filter is always OFF
in double and quad speed modes. The DEM0 pin and DEM0 bit are OR’d in serial control mode. In parallel control mode,
the DEM1 bit is fixed to “0” and only the DEM0 pin can be controlled (44.1kHz or OFF). When in DSD mode, DEM1-0
bits are ignored. The setting value is held even if PCM mode and DSD mode are switched.
No
DEM1
0
0
1
0
2
1
3
1
Table 14. De-emphasis control (Normal Speed Mode)
DEM0
0
1
0
1
Mode
44.1kHz
OFF
48kHz
32kHz
Default
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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