參數(shù)資料
型號(hào)： AK4620BVF
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi)： Codec
英文描述： 24-Bit 192kHz Audio CODEC with IPGA
中文描述： 24位192kHz的音頻編解碼器與單親遺傳算法
文件頁(yè)數(shù)： 17/42頁(yè)
文件大?。?/td> 410K
代理商： AK4620BVF
ASAHI KASEI
[AK4620B]
MS0401-E-00
2005/07
- 17 -
OPERATION OVERVIEW
D/A Conversion Mode
In serial mode, the AK4620B can digitize either PCM data or DSD data. The P/D bit controls PCM/DSD mode. When
DSD mode, DSD data input occurs on DCLK, DSDL and DSDR pins. The ADC and IPGA are in power down mode. In
PCM mode, PCM data input occurs on BICK, SDTI and LRCK pins. When PCM/DSD mode changes (D/P bit), the
AK4620B should be reset by setting RSTAD and RSTDA bits to “0” or by grounding the PDN pin. It takes from 2/fs to
3/fs to change the mode. In parallel mode, AK4620B can only process PCM data.
D/P bit
DAC mode
0
PCM
1
DSD
Table 1. DSD/PCM Mode Control
System Clock Input
1. PCM Mode
AK4620B requires MCLK, BICK and LRCK external clocks. MCLK should be synchronized with LRCK but the phase
is not critical. External clocks (MCLK, BICK and LRCK) should always be present whenever the AK4620B is in normal
operation mode (PDN pin = “H” and either the ADC and DAC is in normal operation mode). If these clocks are not
provided, the AK4620B may draw excess current due to dynamic refresh of internal logic. If the external clocks are not
present, the AK4620B should be in the power-down mode (PDN pin = “L” or power down both the ADC and DAC by the
register). After exiting reset (PDN pin = “L”
“H”) at power-up etc., the AK4620B is in power-down mode until MCLK
and LRCK are provided.
As the AK4620B includes the phase detect circuit for LRCK, the AK4620B is reset automatically when the
synchronization is out of phase by changing the clock frequencies.
1-1. Serial mode (P/S pin= “L”)
As shown in Table 2, Table 3 and Table 4, select the MCLK frequency by setting CMODE, CKS0-1 and DFS0-1
(DFS0 bit and DFS0 pin are internally ORd). These registers are changed when RSTAD bit = RSTDA bit = “0”.
OR of DFS0 bit /
DFS0 pin
0
0
Normal speed
0
1
Double speed
1
0
Quad speed
1
1
Table 2. Sampling speed in serial mode
ADC mode
PCM
Power down
DFS1 bit
Mode
Sampling Rate
32kHz-54kHz
54kHz-108kHz
108kHz-216kHz
-
Default
N/A
相關(guān)PDF資料
PDF描述
AK4626A High Performance Multi-channel Audio CODEC
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AK4628AVQ High Performance Multi-channel Audio CODEC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4620BVFPE2 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:
AK4620BVFP-E2 功能描述:IC AUDIO CODEC 24BIT 30VSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱(chēng):296-21257-2
AK4621 制造商:AKM 制造商全稱(chēng):AKM 功能描述:24-Bit 192kHz Stereo Audio CODEC
AK4621EF 制造商:AKM 制造商全稱(chēng):AKM 功能描述:24-Bit 192kHz Stereo Audio CODEC
AK4621EFP-E2 功能描述:IC AUDIO CODEC 24BIT 30VSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱(chēng):296-21257-2
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