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參數(shù)資料
| 型號(hào)： | AK4588VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 2/8 CHANNEL AUDIO CODEC WITH DIR |
| 中文描述： | 2 / 8聲道音頻編解碼器迪爾 |
| 文件頁數(shù)： | 35/76頁 |
| 文件大?。?/td> | 787K |
| 代理商： | AK4588VQ |
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ASAHI KASEI
[AK4588]
MS0287-E-01
2004/03
- 35 -
Soft mute operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
-
∞
during ATT_DATA
×
ATT transition time (Table 16) from the current ATT level. When the SMUTE bit is returned
to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA
×
ATT
transition time. If the soft mute is cancelled before attenuating to -
∞
after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
Attenuation
DZF1,2
ATT Level
-
∞
AOUT
8192/fs
GD
(2)
GD
(1)
(3)
(4)
(1)
Notes:
(1) ATT_DATA
×
ATT transition time (Table 16). For example, in Normal Speed Mode, this time is 1792LRCK1
cycles (1792/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to 7FH
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -
∞
after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data at all the channels of the group are continuously zeros for 8192 LRCK1 cycles, DZF pin of
each channel goes to “H”. DZF pin immediately goes to “L” if the input data of either channel of the group are
not zero after going DZF “H”.
Figure 13. Soft mute and zero detection
System Reset
The AK4588 should be reset once by bringing PDN pin = “L” upon power-up. The AK4588 is powered up and the
internal timing starts clocking by LRCK1 “
↑
” after exiting reset and power down state by MCLK. The AK4588 is in the
power-down mode until MCLK and LRCK1 are input.
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