- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385093 > AK4588VQ (Asahi Kasei Microsystems Co.,Ltd) 2/8 CHANNEL AUDIO CODEC WITH DIR PDF資料下載
參數(shù)資料
| 型號： | AK4588VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 2/8 CHANNEL AUDIO CODEC WITH DIR |
| 中文描述： | 2 / 8聲道音頻編解碼器迪爾 |
| 文件頁數(shù)： | 25/76頁 |
| 文件大?。?/td> | 787K |
| 代理商： | AK4588VQ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
ASAHI KASEI
[AK4588]
MS0287-E-01
2004/03
- 25 -
OPERATION OVERVIEW (ADC/DAC part)
System Clock
The external clocks, which are required to operate the AK4588, are MCLK, LRCK1 and BICK1. MCLK should be
synchronized with LRCK1 but the phase is not critical. There are two methods to set MCLK frequency. In Manual
Setting Mode (ACKS bit = “0”: Default), the sampling speed is set by DFS1-0 bit (Table 1). The frequency of MCLK at
each sampling speed is set automatically. (Table 3, 4, 5) In Auto Setting Mode (ACKS bit = “1”), as MCLK frequency
is detected automatically (Table 6) and the internal master clock becomes the appropriate frequency (Table 7), it is not
necessary to set DFS1-0 bits.
Only MCLK is necessary in the master mode. Master Clock Input Frequency should be selected by CKS1-0 bits (Table
2), and Sampling Speed should be selected by DFS1-0 bits (Table 1). The frequencies and the duties of the clocks
(LRCK1, BICK1) may not be stabile after setting CKS1-0 bits and DFS1-0 bits up.
External clocks (MCLK, BICK1, LRCK1) should always be present whenever the AK4588 is in normal operation mode
(PDN pin = “H”). If these clocks are not provided, the AK4588 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4588 should be in the power-down
mode (PDN pin = “L”) or in the reset mode (RSTN1 bit = “0”). After exiting reset at power-up etc., the AK4588 is in
the power-down mode until MCLK and LRCK are input.
In the Master mode, External clock(MCLK) should always be supplied except in the power-down mode. It is in
power-down mode until MCLK will be supplied, when Reset was canceled by Power-ON and so on.
DFS1
DFS0
Sampling Speed (fs)
0
0
Normal Speed Mode
0
1
Double Speed Mode
1
0
Quad Speed Mode
Table 1. Sampling Speed (Manual Setting Mode)
CKS1
CKS0
Normal
0
0
256fs
0
1
384fs
1
0
512fs
1
1
256fs
Table 2.Master clock input select (Master Mode)
LRCK1
MCLK (MHz)
Fs
256fs
384fs
32.0kHz
8.1920
12.2880
44.1kHz
11.2896
16.9344
48.0kHz
12.2880
18.4320
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK1
MCLK (MHz)
128fs
192fs
88.2kHz
11.2896
16.9344
96.0kHz
12.2880
18.4320
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
(Note: At Double speed mode (DFS1= “0”, DFS0 = “1”), 128fs and 192fs are not available for ADC.)
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
Default
Double
128fs
192fs
256fs
256fs
Quad
128fs
128fs
128fs
128fs
Default
BICK1 (MHz)
64fs
2.0480
2.8224
3.0720
512fs
16.3840
22.5792
24.5760
BICK1 (MHz)
64fs
5.6448
6.1440
256fs
22.5792
24.5760
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4589VQ | 2/8-Channel Audio CODEC with DIR |
| AK4591 | 24bit 4ch ADC + 24bit 6ch DAC |
| AK4620A | 24 BIT 192KHZ AUDIO CODEC WITH IPGA |
| AK4620AVF | 24 BIT 192KHZ AUDIO CODEC WITH IPGA |
| AK4620B | 24-Bit 192kHz Audio CODEC with IPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4589 | 制造商:AKM 制造商全稱:AKM 功能描述:2/8 CHANNEL AUDIO CODEC WITH DIR |
| AK4589_1 | 制造商:AKM 制造商全稱:AKM 功能描述:2/8-Channel Audio CODEC with DIR |
| AK4589VQ | 制造商:AKM 制造商全稱:AKM 功能描述:2/8-Channel Audio CODEC with DIR |
| AK4591 | 制造商:AKM 制造商全稱:AKM 功能描述:24bit 4ch ADC + 24bit 6ch DAC |
| AK4591VQ | 制造商:AKM 制造商全稱:AKM 功能描述:??￥???????????ˉ??????24bit 4ch ADC 24bit 6ch DAC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。