參數(shù)資料
型號(hào)： AK4565VF
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi)： Codec
英文描述： LOW POWER 20BIT CODEC WITH BUILT IN ALC
中文描述： 低功耗20位編解碼器中的ALC的建造
文件頁(yè)數(shù)： 26/33頁(yè)
文件大?。?/td> 249K
代理商： AK4565VF
ASAHI KASEI
[AK4565]
MS0132-E-01
2003/05
- 26 -
Addr
04H
Register Name
ALC Mode Control 1
R/W
Default
D7
0
D6
0
D5
D4
D3
D2
D1
D0
LMAT1
LMAT0
FDATT RATT1 RATT0
R/W
0
LMTH
0
0
0
0
0
0
0
LMTH: Auto Limiter Detection Level / Auto Recovery Waiting Counter Reset Level
LMTH
ALC Limiter Detection Level
0
ADC Input
≥
–4.0dB
1
ADC Input
≥
–2.0dB
Table 8. Auto Limiter Detection Level / Auto Recovery Waiting Counter Reset Level
ALC Recovery Waiting Counter Reset Level
-4.0dB > ADC Input
≥
-6.0dB
-2.0dB > ADC Input
≥
-4.0dB
Default
RATT1-0: ALC Recovery GAIN Step
During the ALC recovery operation, the number of steps changed from current IPGA value is set. For
example, when the current IPGA value is 30H, RATT1= “0” and RATT0= “1” are set, IPGA changes to
32H by the auto limiter operation, the input signal level is gained by 1dB (=0.5dB x 2).
When the IPGA value exceeds the reference level (REF6-0), the IPGA value does not increase.
RATT1
RATT0
0
0
0
1
1
0
1
1
Table 9. ALC Recovery GAIN Step
FDATT: FADEIN/OUT ATT Step
During the FADEIN/OUT operation, the number of steps changed from current IPGA value is set. For
example, when the current IPGA value is 30H, FDATT = “1” are set, IPGA changes to 32H (FADEIN) or
2EH (FADEOUT) by the FADEIN/OUT operation, the input signal level is gained by 1dB(=0.5dB x 2).
When the IPGA value exceeds the reference level (REF6-0) or 00H, the IPGA value does not increase.
FDATT
ATT Step
0
1
1
2
Table 10. FADEIN/OUT ATT Step
LMAT1-0: ALC Limiter ATT Step
During the ALC limiter operation, when input signal exceeds the ALC limiter detection level set by
LMTH, the number of steps attenuated from current IPGA value is set. For example, when the current
IPGA value is 60H in the state of LMAT1-0 = “11”, it becomes IPGA=5CH by the ALC limiter
operation, the input signal level is attenuated by 2dB (=0.5dB x 4).
The ALC limiter period is set by LTM1-0 bits at ZELMN = “1” and ZTM1-0 bits at ZELMN = “0”.
When the attenuation value exceeds IPGA = “00H” (MUTE), it clips to “00”.
LMAT1
LMAT0
0
0
0
1
1
0
1
1
Table 11. ALC Limiter ATT Step
GAIN Step
1
2
3
4
Default
Default
ATT Step
1
2
3
4
Default
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