參數(shù)資料
型號(hào)： AK4564VQ
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi)： Codec
英文描述： 16BIT CODEC WITH BUILT-IN ALC AND MIC/HP/SPK-AMP
中文描述： 16位編解碼器，配有ALC和麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁(yè)數(shù)： 14/48頁(yè)
文件大小： 382K
代理商： AK4564VQ
ASAHI KASEI
[AK4564]
MS0140-E-01
2002/07
- 14 -
OPERATION OVERVIEW
n
System Clock
The clocks required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs
～
). The master clock (MCLK)
should be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can be
input as 256fs or 384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically.
*fs is sampling frequency.
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4564 may
occur click noise. DAC input data should be “0” to avoid click noise.
All external clocks (MCLK, BCLK and LRCK) should always be present except MIC = ADC = DAC = VCOM = HPP =
SPKP = AOUT1P = AOUT2P = “0” or PDN = “L”. If these clocks are not provided, the AK4564 may draw excess current
and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external
clocks are not present, the AK4564 should be placed in MIC = ADC = DAC = VCOM = HPP = SPKP = AOUT1P =
AOUT2P = “0” or PDN = “L”. However, ADC, DAC and ALC2 are in power-down mode until MCLK, BCLK and
LRCK is input, even if they release a power-down mode by PDN pin or control register. (Refer to the “Power
Management Mode”.)
n
System Reset
AK4564 should be reset once by bringing PDN pin “L” upon power-up. After the system reset operation, the all internal
registers become initial value.
Initializing cycle is 4128/fs=86ms@fs=48kHz. During initializing cycle, the ADC digital data outputs of both channels
are forced to a 2's compliment, “0”. Output data of ADC settles data equivalent for analog input signal after initializing
cycle. This cycle is not for DAC.
n
Digital High Pass Filter
The AK4564 has a Digital High Pass Filter (HPF) to cancel DC-offset in ADC. The cut-off frequency of the HPF is 3.7Hz
at fs=48kHz and it is attenuated to –0.15dB at 20Hz. This cut-off frequency scales with the sampling frequency (fs).
相關(guān)PDF資料
PDF描述
AKD4564 16BIT CODEC WITH BUILT-IN ALC AND MIC/HP/SPK-AMP
AK4565 LOW POWER 20BIT CODEC WITH BUILT IN ALC
AK4565VF LOW POWER 20BIT CODEC WITH BUILT IN ALC
AK4566 20bit Stereo CODEC with built-in IPGA & HP-AMP
AK4566VN 20bit Stereo CODEC with built-in IPGA & HP-AMP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4565 制造商:AKM 制造商全稱(chēng):AKM 功能描述:LOW POWER 20BIT CODEC WITH BUILT IN ALC
AK4565VF 制造商:AKM 制造商全稱(chēng):AKM 功能描述:LOW POWER 20BIT CODEC WITH BUILT IN ALC
AK4566 制造商:AKM 制造商全稱(chēng):AKM 功能描述:20bit Stereo CODEC with built-in IPGA & HP-AMP
AK4566VN 制造商:AKM 制造商全稱(chēng):AKM 功能描述:20bit Stereo CODEC with built-in IPGA & HP-AMP
AK4568AER 功能描述:IC CODEC LOW POWER 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購(gòu)買(mǎi)時(shí)間 標(biāo)準(zhǔn)包裝:1,000
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