參數(shù)資料
型號: AK4562
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: LOW POWER 20BIT CODEC WITH PGA
中文描述: 低功耗20位編解碼器美巡賽
文件頁數(shù): 12/29頁
文件大?。?/td> 167K
代理商: AK4562
ASAHI KASEI
[AK4562]
MS0031-E-00
2000/05
- 12 -
OPERATION OVERVIEW
n
System Clock
The clocks that are required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs
). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care. The frequency of MCLK can be input 256fs or
384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever ADC and DAC are in operation. If
these clocks are not provided, the AK4562 may draw excess current and it is not possible to operate properly because
utilizes dynamic refreshed internally. If the external clocks are not present, the AK4562 should be in the power-down
mode.
n
Audio Data I/F Format
Using SDTO, SDTI, BCLK and LRCK pins are connected to external system. Audio data format has four kinds of mode,
the data format is MSB-first, 2’s compliment. Setting by DIF0-1 bit. The default value is DIF0 = DIF1 = “0”.
No.
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO (ADC)
20bit MSB justified
20bit MSB justified
20bit MSB justified
I
2
S Compatible
SDTI (DAC)
20bit LSB justified
16bit LSB justified
24bit LSB justified
I
2
S Compatible
LRCK
BCLK
40fs
32fs
48fs
40fs
Lch: “H”, Rch: “L”
Lch: “H”, Rch: “L”
Lch: “H”, Rch: “L”
Lch: “L”, Rch: “H”
Table 1. Audio Data Format
LRCK
BCLK(64fs)
SDTO(o)
0
1
2
12
13
14
20
21
31
0
1
2
12
13
14
20
21
31
0
19
1
18
0
19 18
8
7
6
0
19
SDTI(i)
1
18
0
19
12
11
1
18
0
19
12
11
19:MSB, 0:LSB
Lch Data
Rch Data
Don’t Care
Don’t Care
8
7
6
Figure 7. Audio Data Format (No.0)
LRCK
BCLK(64fs)
SDTO(o)
0
1
2
15
16
17
20
21
31
0
1
2
15
16
17
20
21
31
0
19
1
18
0
19 18
5
4
3
0
19
SDTI(i)
1
15
0
12
11
1
15
0
12
11
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
Rch Data
Don’t Care
Don’t Care
5
4
3
Figure 8. Audio Data Format (No.1)
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