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參數(shù)資料
| 型號： | AK4550VT |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | LOW POWER & SMALL PACKAGE 16BIT CODEC |
| 中文描述： | 低功耗 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 102K |
| 代理商： | AK4550VT |
ASAHI KASEI
[AK4550]
M0068-E-01
2000/4
- 13 -
n
Layout Pattern Example
AK4550 requires careful attention to power supply and grounding arrangements to optimize performance.
(Please refer to AKD4550 Evaluation Board layout pattern.)
1.
VDD pin should be supplied from analog power supply on system, and VSS pin should be connected to analog
ground on system. The AK4550 is placed on the analog ground plane, and near the analog ground and digital
ground split. And analog and digital ground planes should be only connected at one point. The connection point
should be near to the AK4550.
2.
VDD pin should be distributed from the point with low impedance of regulator etc.
3.
The series resistors are prevent on the clock lines to reduce overshoot and undershoot. To avoid digital noise
coupling to analog circuit in the AK4550, a 10pF ceramic capacitor on MCLK pin is connected with digital ground.
4.
0.1uF ceramic capacitors of VDD-VSS pins and VCOM-VSS pins should be located as close to the AK4550 as
possible. And these lines should be the shortest connection to pins.
0.1u
2.2n
470
2.2n
470
+
Rch In
Lch In
Analog Supply
2.3
～
3.6V
10u
Controller
Digital Ground
Analog Ground
0.1u
4.7u
VCOM
1
AINR
2
AINL
3
VSS
4
VDD
5
DEM0
6
DEM1
7
SDTO
8
16
15
14
13
12
11
10
9
AOUTR
AOUTL
PWAD
SCLK
MCLK
LRCK
SDTI
AK4550
Top View
PWDA
10P
Reset &Power-down
Mode Control
+
+
+
51
51
51
51
51
Figure 4. Layout Pattern Example
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4550VT-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4550VTP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:16BIT 3V |
| AK4551 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.C FOR AK4551 |
| AK4551VT | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER & SMALL PACKAGE 20BIT CODEC |
| AK4552 | 制造商:AKM 制造商全稱:AKM 功能描述:24bit A/D and D/A converter, |
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