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參數(shù)資料
| 型號(hào)： | AK4550VT |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | LOW POWER & SMALL PACKAGE 16BIT CODEC |
| 中文描述： | 低功耗 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 102K |
| 代理商： | AK4550VT |
ASAHI KASEI
[AK4550]
M0068-E-01
2000/4
- 6 -
SWITCHING CHARACTERISTICS
(Ta=25
°
C; VDD=2.3
～
3.6V; C
L
=20pF)
Parameter
Master Clock Timing
256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
512fs:
Pulse Width Low
Pulse Width High
LRCK Frequency
Duty Cycle
Serial Interface Timing
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “
↑
” (Note 9)
SCLK “
↑
” to LRCK Edge (Note 9)
LRCK Edge to SDTO (MSB)
SCLK “
↓
” to SDTO
SDTI Hold Time
SDTI Setup Time
Reset Timing
PWAD or PWDA Pulse Width
PWAD ”
↑
” to SDTO Valid (Note 10)
Symbol
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
min
2.048
28
28
3.072
23
23
4.096
16
16
8
45
typ
max
12.8
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
%
11.2896
16.9344
22.5792
19.2
25.6
44.1
50
55
tSCK
tSCKL
tSCKH
tLRS
tSLR
tDLR
tDSS
tSDH
tSDS
312.5
130
130
50
50
50
50
80
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPW
tPWV
150
2081
ns
1/fs
Notes: 9. SCLK rising edge must not occur at the same time as LRCK edge.
10. These cycles are the number of LRCK rising from PWAD rising.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4550VT-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4550VTP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:16BIT 3V |
| AK4551 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.C FOR AK4551 |
| AK4551VT | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER & SMALL PACKAGE 20BIT CODEC |
| AK4552 | 制造商:AKM 制造商全稱:AKM 功能描述:24bit A/D and D/A converter, |
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