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參數(shù)資料
| 型號： | AK4538 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16Bit DS CODEC with MIC/HP/SPK-AMP |
| 中文描述： | 16位副編解碼器麥克風/惠普/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 28/70頁 |
| 文件大?。?/td> | 485K |
| 代理商： | AK4538 |
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ASAHI KASEI
[AK4538]
MS0198-E-01
2003/5
- 28 -
[3] Example of ALC1 Operation
Table 15 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB.
fs=8kHz
Data Operation Data Operation Data Operation
1
-4dBFS
1
-4dBFS
00
Don’t use
00
Don’t use
0
Enable
0
Enable
00
16ms
01
fs=16kHz
fs=44.1kHz
Register Name Comment
LMTH
LTM1-0
ZELM
ZTM1-0
Limiter detection Level
Limiter operation period at ZELM = 1
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
Gain of IPGA at ALC1 operation start
Limiter ATT Step
Recovery GAIN Step
ALC1 Enable bit
1
00
0
10
-4dBFS
Don’t use
Enable
11.6ms
16ms
WTM1-0
00
16ms
01
16ms
10
11.6ms
REF6-0
IPGA6-0
LMAT1-0
RATT
ALC1
47H
10H
00
0
1
+27.5dB
0dB
1 step
1 step
Enable
47H
10H
00
0
1
+27.5dB
0dB
1 step
1 step
Enable
47H
10H
00
0
1
+27.5dB
0dB
1 step
1 step
Enable
Table 18. Example of the ALC1 setting
The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1
operation is finished by ALC1 bit = “0” or PMMIC bit = “0”.
LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
IPGA gain at ALC1 operation start can be changed from the default value of IPGA6-0 bits while PMMIC bit is “1” and
ALC1 bit is “0”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.
Manual Mode
* The value of IPGA should be
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (REF6-0)
WR (IPGA6-0)
ALC1 Operation
Note : WR : Write
WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 1
Maximum Gain = +27.5dB
Limiter Detection Level = -4dBFS
ALC2 bit = “1” (default)
(1) Addr=08H, Data=00H
(2) Addr=0AH, Data=47H
(4) Addr=09H, Data=61H
(3) Addr=0BH, Data=10H
Figure 21. Registers set-up sequence at ALC1 operation
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PDF描述 |
|---|---|
| AK4538VN | 16Bit DS CODEC with MIC/HP/SPK-AMP |
| AK4541VQ | AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4541 | AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4543 | AC’97 Rev 2.1 Multimedia Audio CODEC |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4538VN | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit DS CODEC with MIC/HP/SPK-AMP |
| AK4541 | 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4541VQ | 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4543 | 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4543VQ | 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC |
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