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參數資料
| 型號： | AK4538 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16Bit DS CODEC with MIC/HP/SPK-AMP |
| 中文描述： | 16位副編解碼器麥克風/惠普/胰腎聯合移植腺苷 |
| 文件頁數： | 21/70頁 |
| 文件大小： | 485K |
| 代理商： | AK4538 |
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ASAHI KASEI
[AK4538]
MS0198-E-01
2003/5
- 21 -
Master Mode (M/S pin = “H”)
Power down
Power up
Frequency set by PLL1-0
bits (Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Output
BF bit = “0” : 64fs Output
BF bit = “1” : 32fs Output
Output
Table 5. Clock Operation at Master Mode (PLL Mode)
PLL Unlock
Frequency set by PLL1-0 bits
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Unsettling
MCKI pin
Refer to Table 1
MCKO pin
“L”
BICK pin
“L”
“L”
LRCK pin
“L”
“L”
Slave Mode (M/S pin = “L”)
Power down
Power up
Frequency set by PLL1-0
bits (Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Output
Input
Input
Table 6. Clock Operation at Slave Mode (PLL Mode)
PLL Unlock
Frequency set by PLL1-0 bits
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Unsettling
Input
Input
MCKI pin
Refer to Table 1
MCKO pin
“L”
BICK pin
LRCK pin
Fixed to “L” or “H” externally
Fixed to “L” or “H” externally
(2) External mode (PMPLL bit = “0”)
When the PMPLL bit = “0”, the AK4538 works in external clock mode. The MCKO pin outputs a buffered clock of MCKI
input.
For example, when MCKI = 256fs, the sampling frequency is changeable from 7kHz to 48kHz (Table 7).
The MCKO bit controls MCKO output enable. The frequency of MCKO is selectable via register the PS1-0 bits as defined
in Table 8.
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be
changed after LRCK is input in slave mode.
The master clock frequency should be changed only when both the
PMADC and PMDAC bits = “0”.
LRCK and BICK are output from the AK4538 in master mode. The clock to the MCKI pin must not stop during normal
operation (PMPLL bit = “1”). If this clock is not provided, the AK4538 may draw excess current due to its use of internal
dynamically refreshed logic. If the external clocks are not present, place the AK4538 in power-down mode (PMADC bit =
PMDAC bit = “0”).
MCKI, BICK and LRCK clocks are required in slave mode. The master clock (MCKI) should be synchronized with
sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK should always be present
whenever the AK4538 is in normal operation (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided,
the AK4538 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK4538 in power-down mode (PMADC bit = PMDAC bit = “0”).
Mode
FS1
FS0
Sampling Frequency (fs)
0
0
0
1
0
1
2
1
0
3
1
1
Table 7. Sampling Frequency Select (EXT Mode)
MCKI
256fs
512fs
1024fs
256fs
Default
7kHz
～
48kHz
7kHz
～
24kHz
7kHz
～
12kHz
7kHz
～
48kHz
相關PDF資料 |
PDF描述 |
|---|---|
| AK4538VN | 16Bit DS CODEC with MIC/HP/SPK-AMP |
| AK4541VQ | AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4541 | AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4543 | AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4543VQ | AC’97 Rev 2.1 Multimedia Audio CODEC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AK4538VN | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit DS CODEC with MIC/HP/SPK-AMP |
| AK4541 | 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4541VQ | 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4543 | 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4543VQ | 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC |
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