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參數(shù)資料
| 型號： | AK4534VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16Bit CODEC with MIC/HP/SPK-AMP |
| 中文描述： | 16位編解碼器麥克風/惠普/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 19/64頁 |
| 文件大?。?/td> | 443K |
| 代理商： | AK4534VN |
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ASAHI KASEI
[AK4534]
MS0133-E-03
2003/5
- 19 -
n
System Clock
(1) PLL Mode (PMPLL bit = “1”)
A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 and FS2-0 bits (see
Table.2 and Table.3). The frequency of the MCKO output is selectable via the PS1-0 bits registers as defined in Table.4
and the MCKO output enable is controlled by the MCKO bit
.
If PS1-0 bits are changed before LRCK is input,
MCKO is not output. PS1-0 bits should be changed after LRCK is input in slave mode.
The PLL should be powered-up after the X’tal oscillator becomes stable or external master clock is inputted.
If X'tal and
PLL are powered-up at the same time or PLL is powered-up before external master clock is inputted,
the PLL does not start.
It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit=“1”. The PLL needs 40ms
lock time, whenever the sampling frequency changes or the PLL is powered-up (PMPLL bit=“0”
→
“1”).
If the sampling frequency is changed and the PLL goes to unlock state when the DAC is operated(PMDAC bit=“1”), the
DAC data should be soft-muted or “0”. In case of the ADC(PMADC bit = “1”), the ADC data acquired during the
frequency change may be erroneous and therefore should not be used.
LRCK and BICK are output from the AK4534 in master mode. When the clock input to MCKI pin stops during normal
operation (PMPLL bit = “1”), the internal PLL continues to oscillate (a few MHz), and LRCK and BICK outputs go to “L”
(see Table 5).
In slave mode, the LRCK input should be synchronized with MCKO. The master clock (MCKI) should be synchronized
with sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK must be present whenever
the AK4534 is operating (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4534 may draw
excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the
AK4534 in power-down mode (PMADC bit = PMDAC bit = “0”).
Mode
PLL1
PLL0
0
0
0
1
0
1
2
1
0
3
1
1
Table 2. MCKI Input Frequency (PLL Mode)
MCKI
12.288MHz
11.2896MHz
12MHz
N/A
Default
FS2
FS1
FS0
Sampling Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
44.1kHz
22.05kHz
11.025kHz
48kHz
32kHz
24kHz
16kHz
8kHz
Default
Table 3. Sampling Frequency (PLL Mode)
Mode
0
1
2
3
PS1
0
0
1
1
PS0
0
1
0
1
MCKO
256fs
128fs
64fs
32fs
Default
Table 4. MCKO Frequency (PLL Mode, MCKO bit = “1”)
相關PDF資料 |
PDF描述 |
|---|---|
| AK4536 | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4536VN | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4537 | 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4537VN | 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4538 | 16Bit DS CODEC with MIC/HP/SPK-AMP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4534VQ | 功能描述:IC CODEC 16BIT MIC/HP/SPK-AMP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時間 標準包裝:1,000 |
| AK4536 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4536VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4537 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4537VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP |
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