參數(shù)資料
型號: AK4527BVQ
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC
中文描述: 高性能多通道音頻解碼器
文件頁數(shù): 11/33頁
文件大?。?/td> 292K
代理商: AK4527BVQ
ASAHI KASEI
[AK4527B]
MS0056-E-00
2000/10
- 11 -
Parameter
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
” to CCLK “
CCLK “
” to CSN “
Rise Time of CSN
Fall Time of CSN
Rise Time of CCLK
Fall Time of CCLK
Control Interface Timing (I
2
C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 20)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 21)
PDN “
” to SDTO valid (Note 22)
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tR1
tF1
tR2
tF2
200
80
80
40
40
0.025*1/fs
50
50
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
-
4.7
4.0
4.7
4.0
4.7
0
0.25
-
-
4.0
0
100
-
-
-
-
-
-
-
1.0
0.3
-
50
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
tPD
tPDV
150
522
ns
1/fs
Notes: 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
21. The AK4527B can be reset by bringing PDN “L” to “H” upon power-up.
22. These cycles are the number of LRCK rising from PDN rising.
23. I
2
C is a registered trademark of Philips Semiconductors.
Purchase of Asahi Kasei Microsystems Co., Ltd I
2
C components conveys a license under the Philips
I
2
C patent to use the components in the I
2
C system, provided the system conform to the I
2
C
specifications defined by Philips.
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