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參數(shù)資料
| 型號： | AK4525VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 20BIT STEREO ADC & DAC WITH X TAL OSC |
| 中文描述： | 20位立體聲ADC |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 152K |
| 代理商： | AK4525VF |
ASAHI KASEI
[AK4525]
MS0053-E-00
2000/9
- 13 -
n
Power-Down & Reset
The ADC and DAC of AK4525 are placed in the power-down mode by bringing a power down pin, PDN “L” and each
digital filter is also reset at the same time.This reset should always be done after power-up. In case of the ADC, an analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after
516 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Figure 7 shows the power-up
sequence.
ADC Internal
State
PDN
516/fs
Normal Operation
Power-down
Init Cycle
Normal Operation
(1)
The clocks may be stopped.
GD
GD
Clock In
MCLK,LRCK,SCLK
ADC In
(Analog)
“0”data
ADC Out
(Digital)
Normal Operation
Power-down
Normal Operation
DAC Internal
State
“0”data
DAC In
(Digital)
DAC Out
(Analog)
GD
External
Mute
Mute ON
GD
(2)
(2)
(3)
(4)
(5)
(5)
(6)
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(3) ADC output is “0” data at the power-down state.
(4) Small click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if
the click noise influences system application.
(5) Click noise occurs at the edge of PDN.
(6) Please mute the analog output externally if the click noise (5) influences system application.
Figure 7. Power-up Sequence
During the power-down mode, the crystal oscillator is left running. The condition of the outputs are as follows.
SDTO = “L”
MCKO = Clock out
LRCK = “H” (master mode)
SCLK = “L” (master mode)
AOUT = VCOM (VA/2)
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