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參數(shù)資料
| 型號(hào)： | AK4525VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 20BIT STEREO ADC & DAC WITH X TAL OSC |
| 中文描述： | 20位立體聲ADC |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 152K |
| 代理商： | AK4525VF |
ASAHI KASEI
[AK4525]
MS0053-E-00
2000/9
- 10 -
n
Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. The AK4525 supports the master mode. In
this case, SCLK and LRCK are outputs and the frequency of SCLK is fixed to 64fs. Four serial data modes selected by the
DIF0 and DIF1 pins are supported as shown in Table 3. In all modes the serial data has MSB first, 2’s compliment format.
The data is clocked out on the falling edge of SCLK and latched on the rising edge. For mode 3, if SCLK is 32fs, then the
least significant bits will be truncated.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO (ADC)
20bit, MSB justified
20bit, MSB justified
20bit, MSB justified
IIS (I2S)
SDTI (DAC)
16bit, LSB justified
20bit, LSB justified
20bit, MSB justified
IIS (I2S)
L/R
H/L
H/L
H/L
L/H
SCLK (Slave)
≥
32fs
≥
40fs
≥
40fs
32fs or
≥
40fs
Table 2. Serial Data Modes
Note: In master mode, SCLK frequency is fixed to 64fs.
LRCK(i)
SCLK(i:64fs)
SDTO(o)
0
1
2
19
17
18
20
31
0
1
2
19
17
18
20
31
0
19
1
18
0
19
18
3
2
0
19
SDTI(i)
1
14
0
12
11
1
14
0
12
11
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
Rch Data
Don’t Care
Don’t Care
3
2
SCLK(i:32fs)
SDTO(o)
0
1
2
9
10
12
13
15
0
1
2
9
10
12
13
15
0
19
1
18
8
19
18
8
11 10
19
SDTI(i)
1
6
0
4
3
1
15
0
5
4
11
10
2
5
4
7
6
17
15
14 13
3
11
14
9
5
7
17
1
13
15
30
17
3
3
17
14
13
7
6
3
2
15
14
11
4
5
6
7
9
1
15
13
2
2
Figure 2. Mode 0 Timing
LRCK(i)
SCLK(i:64fs)
SDTO(o)
0
1
2
12
13
14
20
21
31
0
1
2
12
13
14
20
21
31
0
19
1
18
0
19 18
8
7
6
0
19
SDTI(i)
1
18
0
19
12
11
1
18
0
19
12
11
19:MSB, 0:LSB
Lch Data
Rch Data
Don’t Care
Don’t Care
8
7
6
Figure 3. Mode 1 Timing
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