參數(shù)資料
型號(hào): AK4524VF
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 24BIT 96KHZ AUDIO CODEC
中文描述: 24位96kHz的音頻編解碼器
文件頁(yè)數(shù): 17/31頁(yè)
文件大?。?/td> 320K
代理商: AK4524VF
ASAHI KASEI
[AK4524]
M0050-E-01
1999/5
- 17 -
n
Power Down & Reset
The ADC and DAC of AK4524 are placed in the power-down mode by bringing a power down pin, PD “L” and each
digital filter is also reset at the same time. The internal register values are initialized by PD “L”. This reset should always
be done after power-up. And then as both control registers of ADC and DAC go reset state (RSTAD=RSTDA=”0”), each
register sholud be cancelled after doing the needed setting. In case of the ADC, an analog initialization cycle starts after
exiting the power-down or reset state. Therefore, the output data, SDTO becomes available after 516 cycles of LRCK
clock. This initialization cycle does not affect the DAC operation. Power down mode can be also controlled by the registers
(PWAD, PWDA).
Power Supply
RSTAD(register)
RSTDA(register)
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
IATT
SDTO
OATT
AOUT
DAC Internal State
External Mute
Example
External clocks
in slave mode
The clocks can be stopped.
PD
Reset INITA
Normal
PD
INITA
Normal
00H
00H
XXH
XXH
00H
00H
XXH
XXH
“0”
“0”
FI
Output
FI
Output
PD
Reset
PD
Normal
Normal
00H
00H
XXH
XXH
00H
00H
XXH
XXH
“0”
“0”
FI
Output
FI
MCLK, LRCK, BICK
PD pin
*
*
*
*
·
INITA:
·
PD:
·
XXH:
·
FI:
·
AOUT:
Initializing period of ADC analog section (516/fs).
Power down state. The contents of all registers are hold.
The current value in ATT register.
Fade in. After exiting power down and reset state, ATT value fades in.
Some pop noise may occur at “*”.
Figure 7. Reset & Power down sequence
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