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參數(shù)資料
| 型號： | AK4523VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 20BIT STEREO ADC & DAC |
| 中文描述： | 20位立體聲ADC |
| 文件頁數(shù)： | 17/20頁 |
| 文件大小： | 161K |
| 代理商： | AK4523VF |
ASAHI KASEI
[AK4523]
M0021-E-03
1999/12
- 17 -
1. Grounding and Power Supply Decoupling
The AK4523 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied
from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is not critical.
AGND and DGND of the AK4523 should be connected to analog ground plane. System analog ground and digital ground
should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors
should be as near to the AK4523 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
The differential voltage between VREFH and AGND sets the analog input/output range. VREFH pin is normally
connected to VA with a 0.1μF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10μF
parallel with a 0.1μF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load
current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM
pins in order to avoid unwanted coupling into the AK4523.
3. Analog Inputs
The ADC inputs are differential and internally biased to the common voltage (VA/2) with 25k
W
(typ) resistance. Figure 7
is a circuit example which analog signal is input by single end. The signal can be input from either positive or negative
input and the input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp. In case of single ended
input, the distortion around full scale degrades compared with differential input. Figure 10 is a circuit example which
analog signal is input to both positive and negative input and the input signal range scales with the supply voltage and
nominally 0.3 x VREFH Vpp. The AK4523 can accept input voltages from AGND to VA. The ADC output data format is
2’s complement. The output code is 7FFFFH(@20bit) for input above a positive full scale and 80000H(@20bit) for input
below a negative fill scale. The ideal code is 00000H(@20bit) with no input signal. The DC offset is removed by the
internal HPF.
The AK4523 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. A simple RC filter (fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have
significant energy at 64fs.
AK4523
AINR+
1.5nF
330
+
Vop=VA=5V
Signal
10k
330
0.1u
22u
4.7k
10k
3.2Vpp
1.5Vpp
2
3
4
5
AINR-
AINL-
AINL+
10k
Vop
4.7k
Vop
4.7k
10u
BIAS
Same circuit
1.5Vpp
NJM2100
+
+
-
-
Figure 10. Differential Input Buffer Example
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相關(guān)代理商/技術(shù)參數(shù) |
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| AK4524 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| AK4524_04 | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 96kHz Audio CODEC |
| AK4524_12 | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 96kHz Audio CODEC |
| AK4524VF | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 96kHz Audio CODEC |
| AK4524VFP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:RECOM REPLC AK4620BVF |
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