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參數(shù)資料
| 型號： | AK4522VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 20BIT STEREO ADC & DAC |
| 中文描述： | 20位立體聲ADC |
| 文件頁數(shù)： | 9/18頁 |
| 文件大小： | 134K |
| 代理商： | AK4522VF |
ASAHI KASEI
[AK4522]
M0020-E-01
1998/10
- 9 -
OPERATION OVERVIEW
n
System Clock
The master clock (MCLK) can be external clock input to the MCKI pin. CMODE is used to select either MCLK=256fs,
384fs or 512fs. The relationship between the MCLK and the desired sample rate is defined in Table 1. The LRCK clock
input must be synchronized with MCLK, however the phase is not critical. Internal timing is synchronized to LRCK upon
power-up. All external clocks must be present unless PD = “L”, otherwise excessive current may result from abnormal
operation of internal dynamic logic.
MCLK
SCLK
fs
256fs
CMODE=”L”
8.1920MHz
11.2896MHz
12.2880MHz
384fs
CMODE=”H”
12.2880MHz
16.9344MHz
18.4320MHz
512fs
CMODE=”NC”
16.384MHz
22.579MHz
24.576MHz
64fs
128fs
32.0kHz
44.1kHz
48.0kHz
2.048MHz
2.822MHz
3.072MHz
4.096MHz
5.644MHz
6.144MHz
Table 1. System Clock Example
n
Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. Four serial data modes selected by the DIF0
and DIF1 pins are supported as shown in Table 2. In all modes the serial data has MSB first, 2’s compliment format. The
data is clocked out on the falling edge of SCLK and latched on the rising edge. For mode 3, if SCLK is 32fs, then the least
significant bits will be truncated.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO (ADC)
20bit, MSB justified
20bit, MSB justified
20bit, MSB justified
IIS (I2S)
SDTI (DAC)
16bit, LSB justified
20bit, LSB justified
20bit, MSB justified
IIS (I2S)
L/R
H/L
H/L
H/L
L/H
SCLK
≥
32fs
≥
40fs
≥
40fs
≥
32fs or 40fs
Table 2. Serial Data Modes
LRCK(i)
SCLK(i:64fs)
SDTO(o)
0
1
2
19
17
18
20
31
0
1
2
19
17
18
20
31
0
19
1
18
0
19
18
3
2
0
19
SDTI(i)
1
14
0
12
11
1
14
0
12
11
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
Rch Data
Don’t Care
Don’t Care
3
2
SCLK(i:32fs)
SDTO(o)
0
1
2
9
10
12
13
15
0
1
2
9
10
12
13
15
0
19
1
18
8
19
18
8
11 10
19
SDTI(i)
1
6
0
4
3
1
15
0
5
4
11
10
2
5
4
7
6
17
15
14 13
3
11
14
9
5
7
17
1
13
15
30
17
3
3
17
14
13
7
6
3
2
15
14
11
4
5
6
7
9
1
15
13
2
2
Figure 1. Mode 0 Timing
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