- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385092 > AK4420 (Asahi Kasei Microsystems Co.,Ltd) 192kHz 24-Bit Stereo ツヒ DAC with 2Vrms Output PDF資料下載
參數(shù)資料
| 型號(hào)： | AK4420 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192kHz 24-Bit Stereo ツヒ DAC with 2Vrms Output |
| 中文描述： | 192kHz的24位立體聲ツヒDAC，具有2Vrms的輸出 |
| 文件頁(yè)數(shù)： | 9/19頁(yè) |
| 文件大小： | 373K |
| 代理商： | AK4420 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)
[AK4420]
OPERATION OVERVIEW
■
System Clock
The external clocks required to operate the AK4420 are MCLK, LRCK and BICK. The master clock (MCLK) should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the internal master
clock is set to the appropriate frequency (
Table 1
).
The AK4420 is automatically placed in power saving mode when MCLK and LRCK stop during normal operation mode,
and the analog output is forced to 0V(typ). When MCLK and LRCK are input again, the AK4420 is powered up. After
power-up, the AK4420 is in the power-down mode until MCLK and LRCK are input.
LRCK
MCLK (MHz)
fs
128fs
192fs
256fs
384fs
32.0kHz
-
-
-
-
44.1kHz
-
-
-
-
48.0kHz
-
-
-
-
32.0kHz
8.192
12.288
44.1kHz
11.2896
16.9344
48.0kHz
12.288
18.432
88.2kHz
-
-
22.5792
33.8688
96.0kHz
-
-
24.5760
36.8640
176.4kHz
22.5792
33.8688
-
-
192.0kHz
24.5760
36.8640
-
-
Table 1. system clock example
When MCLK= 256fs/384fs, the AK4420 supports sampling rate of 32kHz~96kHz (
Table 2
). But, when the sampling rate
is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
MCLK
256fs/384fs
512fs/768fs
Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
■
Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The DIF pin can select between two serial
data modes as shown in
Table 3
. In all modes the serial data is MSB-first, two’s complement format and it is latched on
the rising edge of BICK. In one cycle of LRCK, eight “H” pulses or more must not be input to the DIF pin.
Mode
DIF
SDTI Format
0
L
24bit MSB justified
1
H
24bit I
2
S
Table 3. Audio Data Formats
512fs
16.3840
22.5792
24.5760
-
-
-
-
768fs
24.5760
33.8688
36.8640
-
-
-
-
1152fs
36.8640
-
-
Sampling
Speed
Normal
-
-
-
-
Double
Quad
DR,S/N
102dB
105dB
BICK
≥
48fs
≥
48fs
Figure
Figure 3
Figure 4
MS0683-E-02
2007/12
- 9 -
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4420ET | 192kHz 24-Bit Stereo ツヒ DAC with 2Vrms Output |
| AK4516A | 3V 16bit ADC & DAC with built-in PGA(3V 16位帶內(nèi)置的模擬輸入可編程增益放大器的A/D轉(zhuǎn)換器和D/A轉(zhuǎn)換器) |
| AK4516AVF | 3V 16BIT ADC&DAC WITH BUILT-IN PGA |
| AK4522 | 20BIT STEREO ADC & DAC |
| AK4522VF | 20BIT STEREO ADC & DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4420_10 | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output |
| AK4420ET | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output |
| AK4420ETP-E2 | 功能描述:IC DAC 24BIT STEREO 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AK4420VT | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output |
| AK4421 | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。