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參數(shù)資料
| 型號(hào)： | AK4396 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Advanced Multi-Bit 192kHz 24-Bit ツヒ DAC |
| 中文描述： | 先進(jìn)的多位192kHz的24位數(shù)模轉(zhuǎn)換器ツヒ |
| 文件頁(yè)數(shù)： | 27/38頁(yè) |
| 文件大小： | 435K |
| 代理商： | AK4396 |
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ASAHI KASEI
[AK4396]
MS0336-E-00
2004/08
- 27 -
Register Control Interface
Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4396. In parallel mode,
the register setting is ignored and the pin setting is ignored in serial mode. When the state of P/S pin is changed, the
AK4396 should be reset by PDN pin. The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting
must be all “L”. Internal registers may be written by 3-wire μP interface pins: CSN, CCLK and CDTI. The data on this
interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits)
and Control data (MSB first, 8bits). The AK4396 latches the data on the rising edge of CCLK, so data should be clocked
in on the falling edge. The writing of data becomes valid by CSN “
↑
”. The clock speed of CCLK is 5MHz (max).
Function
Parallel mode
Auto Setting Mode
Manual Setting Mode
Audio Format
De-emphasis
SMUTE
DSD Mode
Zero Detection
Slow roll-off response
Digital Attenuator
Table 14. Function List (O: Available, X: Not available)
PDN pin = “L” resets the registers to their default values. In serial mode, the internal timing circuit is reset by RSTN bit,
but the registers are not initialized.
CSN
Serial mode
O
O
O
O
O
O
O
O
O
O
O
O
O
O
X
X
X
X
CDTI
CCLK
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 11. Control I/F Timing
* The AK4396 does not support the read command.
* When the AK4396 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
* The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is “L”.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4396VF | Advanced Multi-Bit 192kHz 24-Bit ツヒ DAC |
| AK4397 | High Performance Premium 32-Bit DAC |
| AK4397EQ | High Performance Premium 32-Bit DAC |
| AK4420 | 192kHz 24-Bit Stereo ツヒ DAC with 2Vrms Output |
| AK4420ET | 192kHz 24-Bit Stereo ツヒ DAC with 2Vrms Output |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4396VF | 制造商:AKM 制造商全稱:AKM 功能描述:Advanced Multi-Bit 192kHz 24-Bit ツヒ DAC |
| AK4396VFP-E2 | 功能描述:IC DAC 24BIT STEREO 28VSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AK4397 | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz sampling 32Bit ツヒ DAC |
| AK4397EQ | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance Premium 32-Bit DAC |
| AK4399 | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 123dB Premium 32-Bit DAC |
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