參數(shù)資料
型號(hào)： AK4396
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Advanced Multi-Bit 192kHz 24-Bit ツヒ DAC
中文描述： 先進(jìn)的多位192kHz的24位數(shù)模轉(zhuǎn)換器ツヒ
文件頁(yè)數(shù)： 24/38頁(yè)
文件大小： 435K
代理商： AK4396
ASAHI KASEI
[AK4396]
MS0336-E-00
2004/08
- 24 -
Zero Detection
The AK4396 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF pin “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF
pins of both channels go to “L” at 4 ~ 5/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both
channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect
function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the
polarity of DZF pin.
Soft
Mute
operation
Soft mute operation is performed at digital domain. When SMUTE pin goes to “H” or SMUTE bit goes to “1”, the output
signal is attenuated by
∞
during ATT_DATA
×
ATT transition time (Table 13) from the current ATT level. When
SMUTE pin is returned to “L” or SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually
changes to the ATT level during ATT_DATA
×
ATT transition time. If the soft mute is cancelled before attenuating
∞
after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is
effective for changing the signal source without stopping the signal transmission.
SMUTE pin or
SMUTE bit
(1)
Attenuation
DZF pin
ATT_Level
-
∞
AOUT
8192/fs
GD
(2)
GD
(2)
(3)
(4)
(1)
Notes:
(1) ATT_DATA
×
ATT transition time (Table 13). For example, this time is 1020LRCK cycles (1020/fs)
at ATT_DATA=255 in Normal Speed Mode.
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled before attenuating
∞
after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes
to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”.
Figure 8. Soft Mute and Zero Detection
System Reset
The AK4396 should be reset once by bringing PDN pin = “L” upon power-up. The analog section exits power-down
mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during
4/fs.
相關(guān)PDF資料
PDF描述
AK4396VF Advanced Multi-Bit 192kHz 24-Bit ツヒ DAC
AK4397 High Performance Premium 32-Bit DAC
AK4397EQ High Performance Premium 32-Bit DAC
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AK4420ET 192kHz 24-Bit Stereo ツヒ DAC with 2Vrms Output
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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