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參數(shù)資料
| 型號(hào)： | AK4393VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | ADVANCED MULTI-BIT 96KHZ 24-BIT DAC |
| 中文描述： | 先進(jìn)的多位96kHz的24位DAC |
| 文件頁(yè)數(shù)： | 16/22頁(yè) |
| 文件大?。?/td> | 235K |
| 代理商： | AK4393VF |
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ASAHI KASEI
[AK4393]
M0039-E-01
2000/5
- 16 -
n
Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
01H
02H
Notes:
Control 1
Control 2
Test
0
0
CKS2
0
TEST6
CKS1
0
TEST5
CKS0
0
TEST4
DIF2
DFS
TEST3
DIF1
DEM1
TEST2
DIF0
DEM0
TEST1
RSTN
SMUTE
TEST0
TEST7
For addresses from 03H to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the only
internal timing is reset and the registers are not initialized to their default values. DIF2-0, CKS2-0 and DFS bits are
ORed with pins respectively.
n
Register Definitions
Addr
00H
Register Name
Control 1
default
D7
0
0
D6
CKS2
0
D5
CKS1
0
D4
CKS0
0
D3
DIF2
0
D2
DIF1
0
D1
DIF0
0
D0
RSTN
1
RSTN: Internal timing reset
0: Reset. All registers are not initialized.
1: Normal Operation
When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.
DIF2-0: Audio data interface modes (see Table 5)
Initial: “000”, Mode 0
Register bits are ORed with DIF2-0 pins if P/S = “L”.
CKS2-0: Master Clock Frequency Select (see Table 2)
Initial: “000”, Mode 0
Register bits are ORed with CKS2-0 pins if P/S = “L”.
Addr
01H
Register Name
Control 2
default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
DFS
0
D2
D1
D0
DEM1
0
DEM0
0
SMUTE
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis response (see Table 6)
Initial: “00”, 44.1kHz
DFS: Sampling speed control (see Table 1)
0: Normal speed
1: Double speed
Register bit is ORed with DFS pin if P/S = “L”.
Addr
02H
Register Name
Test
default
D7
D6
D5
D4
D3
D2
D1
D0
TEST7
0
TEST6
0
TEST5
0
TEST4
0
TEST3
0
TEST2
0
TEST1
0
TEST0
0
TEST7-0: Test mode. Do not write any data to 02H.
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